📄 mymain.rpt
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| | | | | | | +----------------- LC19 OUT22
| | | | | | | | +--------------- LC18 OUT23
| | | | | | | | | +------------- LC17 OUT30
| | | | | | | | | | +----------- LC21 OUT40
| | | | | | | | | | | +--------- LC22 OUT41
| | | | | | | | | | | | +------- LC23 OUT42
| | | | | | | | | | | | | +----- LC24 OUT43
| | | | | | | | | | | | | | +--- LC25 TRINGLE_BRANCH
| | | | | | | | | | | | | | | +- LC26 TRINGLE_MAIN
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
Pin
7 -> - * * * * * * - - * * * * * * * | - * | <-- incount0
4 -> * * * * * * * - * * * * * * * * | * * | <-- incount1
6 -> * * * * * * * * * * * * * * * * | - * | <-- incount2
5 -> * * * * * * * * * * * * * * * * | * * | <-- incount3
8 -> * * * * * * * - * * * * * * * * | - * | <-- incount4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\lon\4_what\mymain.rpt
mymain
** EQUATIONS **
incount0 : INPUT;
incount1 : INPUT;
incount2 : INPUT;
incount3 : INPUT;
incount4 : INPUT;
-- Node name is 'DIGSELECT_BRANCH'
-- Equation name is 'DIGSELECT_BRANCH', location is LC020, type is output.
DIGSELECT_BRANCH = LCELL( _EQ001 $ !incount3);
_EQ001 = incount1 & incount2 & !incount3 & incount4
# incount3 & !incount4;
-- Node name is 'DIGSELECT_MAIN'
-- Equation name is 'DIGSELECT_MAIN', location is LC030, type is output.
DIGSELECT_MAIN = LCELL( _EQ002 $ !incount3);
_EQ002 = incount0 & incount2 & incount3 & !incount4
# !incount0 & incount1 & incount3 & !incount4
# !incount1 & !incount2 & incount3 & !incount4;
-- Node name is 'maingreen'
-- Equation name is 'maingreen', location is LC031, type is output.
maingreen = LCELL( _EQ003 $ GND);
_EQ003 = incount0 & incount1 & incount3 & !incount4
# incount2 & incount3 & !incount4
# !incount3 & incount4;
-- Node name is 'mainred'
-- Equation name is 'mainred', location is LC028, type is output.
mainred = LCELL( _EQ004 $ !incount4);
_EQ004 = incount0 & incount2 & incount3 & !incount4
# incount1 & incount2 & incount3 & !incount4;
-- Node name is 'mainyellow'
-- Equation name is 'mainyellow', location is LC029, type is output.
mainyellow = LCELL( _EQ005 $ !incount3);
_EQ005 = incount0 & incount2 & incount3 & !incount4
# !incount0 & incount1 & incount3 & !incount4
# !incount1 & !incount2 & incount3 & !incount4;
-- Node name is 'OUT10'
-- Equation name is 'OUT10', location is LC032, type is output.
OUT10 = LCELL( _EQ006 $ GND);
_EQ006 = incount0 & !incount1 & incount2 & incount3 & !incount4;
-- Node name is 'OUT11'
-- Equation name is 'OUT11', location is LC012, type is output.
OUT11 = LCELL( GND $ GND);
-- Node name is 'OUT12'
-- Equation name is 'OUT12', location is LC007, type is output.
OUT12 = LCELL( GND $ GND);
-- Node name is 'OUT13'
-- Equation name is 'OUT13', location is LC008, type is output.
OUT13 = LCELL( GND $ GND);
-- Node name is 'OUT20'
-- Equation name is 'OUT20', location is LC027, type is output.
OUT20 = LCELL( _EQ007 $ GND);
_EQ007 = !incount0 & incount1 & incount2 & incount3 & !incount4
# !incount0 & !incount3;
-- Node name is 'OUT21'
-- Equation name is 'OUT21', location is LC006, type is output.
OUT21 = LCELL( _EQ008 $ GND);
_EQ008 = !incount1 & !incount3;
-- Node name is 'OUT22'
-- Equation name is 'OUT22', location is LC019, type is output.
OUT22 = LCELL( _EQ009 $ GND);
_EQ009 = !incount2 & !incount3;
-- Node name is 'OUT23'
-- Equation name is 'OUT23', location is LC018, type is output.
OUT23 = LCELL( _EQ010 $ GND);
_EQ010 = incount1 & incount2 & incount3 & !incount4;
-- Node name is 'OUT30'
-- Equation name is 'OUT30', location is LC017, type is output.
OUT30 = LCELL( _EQ011 $ GND);
_EQ011 = !incount0 & incount1 & !incount2 & !incount3 & !incount4
# !incount1 & !incount2 & !incount3 & !incount4;
-- Node name is 'OUT31'
-- Equation name is 'OUT31', location is LC009, type is output.
OUT31 = LCELL( GND $ GND);
-- Node name is 'OUT32'
-- Equation name is 'OUT32', location is LC010, type is output.
OUT32 = LCELL( GND $ GND);
-- Node name is 'OUT33'
-- Equation name is 'OUT33', location is LC011, type is output.
OUT33 = LCELL( GND $ GND);
-- Node name is 'OUT40'
-- Equation name is 'OUT40', location is LC021, type is output.
OUT40 = LCELL( _EQ012 $ GND);
_EQ012 = incount0 & !incount1 & !incount2 & !incount3 & incount4
# incount0 & !incount4;
-- Node name is 'OUT41'
-- Equation name is 'OUT41', location is LC022, type is output.
OUT41 = LCELL( _EQ013 $ VCC);
_EQ013 = incount0 & incount1 & _X001
# incount2 & incount3 & _X002
# !incount2 & !incount3 & _X003
# !incount0 & !incount1 & _X004
# incount4 & _X003;
_X001 = EXP( incount2 & incount3);
_X002 = EXP( incount0 & incount1);
_X003 = EXP(!incount0 & !incount1);
_X004 = EXP(!incount2 & !incount3);
-- Node name is 'OUT42'
-- Equation name is 'OUT42', location is LC023, type is output.
OUT42 = LCELL( _EQ014 $ GND);
_EQ014 = incount0 & !incount1 & incount2 & incount3 & !incount4
# !incount0 & !incount1 & !incount2 & incount3 & !incount4
# incount0 & incount2 & !incount3 & !incount4
# !incount0 & incount1 & incount2 & !incount4;
-- Node name is 'OUT43'
-- Equation name is 'OUT43', location is LC024, type is output.
OUT43 = LCELL( _EQ015 $ GND);
_EQ015 = incount0 & incount1 & !incount2 & !incount3 & !incount4
# !incount0 & !incount1 & incount2 & !incount3 & !incount4;
-- Node name is 'TRINGLE_BRANCH'
-- Equation name is 'TRINGLE_BRANCH', location is LC025, type is output.
TRINGLE_BRANCH = LCELL( _EQ016 $ GND);
_EQ016 = incount0 & incount1 & !incount2 & !incount3 & incount4
# !incount1 & incount2 & !incount3 & incount4;
-- Node name is 'TRINGLE_MAIN'
-- Equation name is 'TRINGLE_MAIN', location is LC026, type is output.
TRINGLE_MAIN = LCELL( _EQ017 $ GND);
_EQ017 = !incount0 & incount1 & !incount2 & incount3 & !incount4
# !incount1 & !incount2 & incount3 & !incount4;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\lon\4_what\mymain.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,070K
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