📄 mymain.rpt
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Project Information e:\lon\4_what\mymain.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/09/2006 19:44:10
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mymain EPM7032LC44-6 5 23 0 23 4 71 %
User Pins: 5 23 0
Project Information e:\lon\4_what\mymain.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'OUT13' is stuck at GND
Warning: Primitive 'OUT12' is stuck at GND
Warning: Primitive 'OUT11' is stuck at GND
Warning: Primitive 'OUT33' is stuck at GND
Warning: Primitive 'OUT32' is stuck at GND
Warning: Primitive 'OUT31' is stuck at GND
Device-Specific Information: e:\lon\4_what\mymain.rpt
mymain
***** Logic for device 'mymain' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
i i i
n n n
c c c
o o o O O
u u u U U
n n n V G G G G G T T
t t t C N N N N N 3 2
2 3 1 C D D D D D 0 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
incount0 | 7 39 | OUT22
incount4 | 8 38 | DIGSELECT_BRANCH
OUT21 | 9 37 | OUT40
GND | 10 36 | OUT41
OUT12 | 11 35 | VCC
OUT13 | 12 EPM7032LC44-6 34 | OUT42
OUT31 | 13 33 | OUT43
OUT32 | 14 32 | TRINGLE_BRANCH
VCC | 15 31 | TRINGLE_MAIN
OUT33 | 16 30 | GND
OUT11 | 17 29 | OUT20
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V O m D m m
E E E E N C U a I a a
S S S S D C T i G i i
E E E E 1 n S n n
R R R R 0 g E y r
V V V V r L e e
E E E E e E l d
D D D D e C l
n T o
_ w
M
A
I
N
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\lon\4_what\mymain.rpt
mymain
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 7/16( 43%) 12/16( 75%) 0/16( 0%) 2/36( 5%)
B: LC17 - LC32 16/16(100%) 16/16(100%) 5/16( 31%) 5/36( 13%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 28/32 ( 87%)
Total logic cells used: 23/32 ( 71%)
Total shareable expanders used: 4/32 ( 12%)
Total Turbo logic cells used: 23/32 ( 71%)
Total shareable expanders not available (n/a): 1/32 ( 3%)
Average fan-in: 3.34
Total fan-in: 77
Total input pins required: 5
Total output pins required: 23
Total bidirectional pins required: 0
Total logic cells required: 23
Total flipflops required: 0
Total product terms required: 52
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\lon\4_what\mymain.rpt
mymain
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
7 (4) (A) INPUT 0 0 0 0 0 13 0 incount0
4 (1) (A) INPUT 0 0 0 0 0 16 0 incount1
6 (3) (A) INPUT 0 0 0 0 0 16 0 incount2
5 (2) (A) INPUT 0 0 0 0 0 17 0 incount3
8 (5) (A) INPUT 0 0 0 0 0 15 0 incount4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\lon\4_what\mymain.rpt
mymain
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
38 20 B OUTPUT t 0 0 0 4 0 0 0 DIGSELECT_BRANCH
26 30 B OUTPUT t 0 0 0 5 0 0 0 DIGSELECT_MAIN
25 31 B OUTPUT t 0 0 0 5 0 0 0 maingreen
28 28 B OUTPUT t 0 0 0 5 0 0 0 mainred
27 29 B OUTPUT t 0 0 0 5 0 0 0 mainyellow
24 32 B OUTPUT t 0 0 0 5 0 0 0 OUT10
17 12 A OUTPUT t 0 0 0 0 0 0 0 OUT11
11 7 A OUTPUT t 0 0 0 0 0 0 0 OUT12
12 8 A OUTPUT t 0 0 0 0 0 0 0 OUT13
29 27 B OUTPUT t 0 0 0 5 0 0 0 OUT20
9 6 A OUTPUT t 0 0 0 2 0 0 0 OUT21
39 19 B OUTPUT t 0 0 0 2 0 0 0 OUT22
40 18 B OUTPUT t 0 0 0 4 0 0 0 OUT23
41 17 B OUTPUT t 0 0 0 5 0 0 0 OUT30
13 9 A OUTPUT t 0 0 0 0 0 0 0 OUT31
14 10 A OUTPUT t 0 0 0 0 0 0 0 OUT32
16 11 A OUTPUT t 0 0 0 0 0 0 0 OUT33
37 21 B OUTPUT t 0 0 0 5 0 0 0 OUT40
36 22 B OUTPUT t 5 0 1 5 0 0 0 OUT41
34 23 B OUTPUT t 0 0 0 5 0 0 0 OUT42
33 24 B OUTPUT t 0 0 0 5 0 0 0 OUT43
32 25 B OUTPUT t 0 0 0 5 0 0 0 TRINGLE_BRANCH
31 26 B OUTPUT t 0 0 0 5 0 0 0 TRINGLE_MAIN
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\lon\4_what\mymain.rpt
mymain
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC12 OUT11
| +----------- LC7 OUT12
| | +--------- LC8 OUT13
| | | +------- LC6 OUT21
| | | | +----- LC9 OUT31
| | | | | +--- LC10 OUT32
| | | | | | +- LC11 OUT33
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B | Logic cells that feed LAB 'A':
Pin
4 -> - - - * - - - | * * | <-- incount1
5 -> - - - * - - - | * * | <-- incount3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\lon\4_what\mymain.rpt
mymain
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC20 DIGSELECT_BRANCH
| +----------------------------- LC30 DIGSELECT_MAIN
| | +--------------------------- LC31 maingreen
| | | +------------------------- LC28 mainred
| | | | +----------------------- LC29 mainyellow
| | | | | +--------------------- LC32 OUT10
| | | | | | +------------------- LC27 OUT20
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