📄 count3.rpt
字号:
count3
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 04 DFFE + 0 0 1 3 count0
- 4 - B 04 DFFE + 0 2 1 2 count1
- 1 - B 04 DFFE + 0 3 1 1 count2
- 5 - B 04 DFFE + 0 2 1 2 COUNT3
- 2 - B 04 DFFE + 0 2 1 2 count4
- 7 - B 04 OR2 0 3 0 2 :45
- 6 - B 04 OR2 ! 0 3 0 3 :56
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\4_monday\count3.rpt
count3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\4_monday\count3.rpt
count3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: e:\4_monday\count3.rpt
count3
** EQUATIONS **
clk : INPUT;
-- Node name is 'count0' from file "count3.tdf" line 8, column 6
-- Equation name is 'count0', location is LC3_B4, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'count1' from file "count3.tdf" line 8, column 6
-- Equation name is 'count1', location is LC4_B4, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !count0 & count1 & _LC7_B4
# count0 & !count1 & _LC7_B4;
-- Node name is 'count2' from file "count3.tdf" line 8, column 6
-- Equation name is 'count2', location is LC1_B4, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !count1 & count2 & _LC7_B4
# !count0 & count2 & _LC7_B4
# count0 & count1 & !count2 & _LC7_B4;
-- Node name is 'COUNT3' from file "count3.tdf" line 8, column 6
-- Equation name is 'COUNT3', location is LC5_B4, type is buried.
COUNT3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = COUNT3 & !_LC6_B4
# !COUNT3 & !count4 & _LC6_B4;
-- Node name is 'count4' from file "count3.tdf" line 8, column 6
-- Equation name is 'count4', location is LC2_B4, type is buried.
count4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = COUNT3 & !count4 & _LC6_B4
# count4 & !_LC6_B4;
-- Node name is 'q0' from file "count3.tdf" line 15, column 2
-- Equation name is 'q0', type is output
q0 = count0;
-- Node name is 'q1' from file "count3.tdf" line 15, column 2
-- Equation name is 'q1', type is output
q1 = count1;
-- Node name is 'q2' from file "count3.tdf" line 15, column 2
-- Equation name is 'q2', type is output
q2 = count2;
-- Node name is 'q3' from file "count3.tdf" line 15, column 2
-- Equation name is 'q3', type is output
q3 = COUNT3;
-- Node name is 'q4' from file "count3.tdf" line 15, column 2
-- Equation name is 'q4', type is output
q4 = count4;
-- Node name is ':45' from file "count3.tdf" line 12, column 13
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = LCELL( _EQ005);
_EQ005 = !_LC6_B4
# !count4
# COUNT3;
-- Node name is ':56' from file "count3.tdf" line 13, column 25
-- Equation name is '_LC6_B4', type is buried
!_LC6_B4 = _LC6_B4~NOT;
_LC6_B4~NOT = LCELL( _EQ006);
_EQ006 = !count2
# !count1
# !count0;
Project Information e:\4_monday\count3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,598K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -