digselector.rpt

这个是个模拟红灯实验的

01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      4/24( 16%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
24:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                       e:\4_monday\digselector.rpt
digselector

** EQUATIONS **

clk0     : INPUT;
clk1     : INPUT;
clk2     : INPUT;
digin10  : INPUT;
digin11  : INPUT;
digin12  : INPUT;
digin13  : INPUT;
digin20  : INPUT;
digin21  : INPUT;
digin22  : INPUT;
digin23  : INPUT;
digin30  : INPUT;
digin31  : INPUT;
digin32  : INPUT;
digin33  : INPUT;
digin40  : INPUT;
digin41  : INPUT;
digin42  : INPUT;
digin43  : INPUT;
hour10   : INPUT;
hour11   : INPUT;
hour12   : INPUT;
hour13   : INPUT;
hour20   : INPUT;
hour21   : INPUT;
hour22   : INPUT;
hour23   : INPUT;
NIGHT_MODE : INPUT;

-- Node name is 'digout0' from file "digselector.tdf" line 36, column 38
-- Equation name is 'digout0', type is output 
digout0  =  _LC7_A16;

-- Node name is 'digout1' from file "digselector.tdf" line 36, column 38
-- Equation name is 'digout1', type is output 
digout1  =  _LC8_A16;

-- Node name is 'digout2' from file "digselector.tdf" line 36, column 38
-- Equation name is 'digout2', type is output 
digout2  =  _LC2_C13;

-- Node name is 'digout3' from file "digselector.tdf" line 36, column 38
-- Equation name is 'digout3', type is output 
digout3  =  _LC7_C13;

-- Node name is 'out0' from file "digselector.tdf" line 28, column 24
-- Equation name is 'out0', type is output 
out0     =  _LC3_A24;

-- Node name is 'out1' from file "digselector.tdf" line 29, column 24
-- Equation name is 'out1', type is output 
out1     =  _LC5_A24;

-- Node name is 'out2' from file "digselector.tdf" line 30, column 24
-- Equation name is 'out2', type is output 
out2     =  _LC1_A24;

-- Node name is 'out3' from file "digselector.tdf" line 31, column 24
-- Equation name is 'out3', type is output 
out3     =  _LC2_A24;

-- Node name is 'out4' from file "digselector.tdf" line 35, column 24
-- Equation name is 'out4', type is output 
out4     = !_LC8_A24;

-- Node name is 'out5' from file "digselector.tdf" line 36, column 24
-- Equation name is 'out5', type is output 
out5     = !_LC6_A24;

-- Node name is ':69' from file "digselector.tdf" line 28, column 1
-- Equation name is '_LC3_A24', type is buried 
_LC3_A24 = LCELL( _EQ001);
  _EQ001 = !clk0 & !clk1 & !clk2 & !NIGHT_MODE;

-- Node name is ':81' from file "digselector.tdf" line 29, column 1
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = LCELL( _EQ002);
  _EQ002 =  clk0 & !clk1 & !clk2 & !NIGHT_MODE;

-- Node name is ':97' from file "digselector.tdf" line 30, column 1
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = LCELL( _EQ003);
  _EQ003 = !clk0 &  clk1 & !clk2 & !NIGHT_MODE;

-- Node name is ':114' from file "digselector.tdf" line 31, column 1
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = LCELL( _EQ004);
  _EQ004 =  clk0 &  clk1 & !clk2 & !NIGHT_MODE;

-- Node name is ':127' from file "digselector.tdf" line 35, column 9
-- Equation name is '_LC8_A24', type is buried 
!_LC8_A24 = _LC8_A24~NOT;
_LC8_A24~NOT = LCELL( _EQ005);
  _EQ005 = !clk0 & !clk1 &  clk2;

-- Node name is ':144' from file "digselector.tdf" line 36, column 9
-- Equation name is '_LC6_A24', type is buried 
!_LC6_A24 = _LC6_A24~NOT;
_LC6_A24~NOT = LCELL( _EQ006);
  _EQ006 =  clk0 & !clk1 &  clk2;

-- Node name is '~148~1' from file "digselector.tdf" line 36, column 44
-- Equation name is '~148~1', location is LC1_A16, type is buried.
-- synthesized logic cell 
_LC1_A16 = LCELL( _EQ007);
  _EQ007 =  digin10 &  _LC5_A24
         #  digin20 &  _LC3_A24;

-- Node name is '~148~2' from file "digselector.tdf" line 36, column 44
-- Equation name is '~148~2', location is LC2_A16, type is buried.
-- synthesized logic cell 
_LC2_A16 = LCELL( _EQ008);
  _EQ008 =  digin30 &  _LC2_A24
         #  digin40 &  _LC1_A24;

-- Node name is '~148~3' from file "digselector.tdf" line 36, column 44
-- Equation name is '~148~3', location is LC3_A16, type is buried.
-- synthesized logic cell 
_LC3_A16 = LCELL( _EQ009);
  _EQ009 =  hour20 & !_LC8_A24
         #  hour10 & !_LC6_A24;

-- Node name is ':148' from file "digselector.tdf" line 36, column 44
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ010);
  _EQ010 =  _LC1_A16
         #  _LC2_A16
         #  _LC3_A16;

-- Node name is '~151~1' from file "digselector.tdf" line 36, column 44
-- Equation name is '~151~1', location is LC4_A16, type is buried.
-- synthesized logic cell 
_LC4_A16 = LCELL( _EQ011);
  _EQ011 =  digin11 &  _LC5_A24
         #  digin21 &  _LC3_A24;

-- Node name is '~151~2' from file "digselector.tdf" line 36, column 44
-- Equation name is '~151~2', location is LC5_A16, type is buried.
-- synthesized logic cell 
_LC5_A16 = LCELL( _EQ012);
  _EQ012 =  digin31 &  _LC2_A24
         #  digin41 &  _LC1_A24;

-- Node name is '~151~3' from file "digselector.tdf" line 36, column 44
-- Equation name is '~151~3', location is LC6_A16, type is buried.
-- synthesized logic cell 
_LC6_A16 = LCELL( _EQ013);
  _EQ013 =  hour21 & !_LC8_A24
         #  hour11 & !_LC6_A24;

-- Node name is ':151' from file "digselector.tdf" line 36, column 44
-- Equation name is '_LC8_A16', type is buried 
_LC8_A16 = LCELL( _EQ014);
  _EQ014 =  _LC4_A16
         #  _LC5_A16
         #  _LC6_A16;

-- Node name is '~154~1' from file "digselector.tdf" line 36, column 44
-- Equation name is '~154~1', location is LC1_C13, type is buried.
-- synthesized logic cell 
_LC1_C13 = LCELL( _EQ015);
  _EQ015 =  digin12 &  _LC5_A24
         #  digin22 &  _LC3_A24;

-- Node name is '~154~2' from file "digselector.tdf" line 36, column 44
-- Equation name is '~154~2', location is LC3_C13, type is buried.
-- synthesized logic cell 
_LC3_C13 = LCELL( _EQ016);
  _EQ016 =  digin32 &  _LC2_A24
         #  digin42 &  _LC1_A24;

-- Node name is '~154~3' from file "digselector.tdf" line 36, column 44
-- Equation name is '~154~3', location is LC4_C13, type is buried.
-- synthesized logic cell 
_LC4_C13 = LCELL( _EQ017);
  _EQ017 =  hour22 & !_LC8_A24
         #  hour12 & !_LC6_A24;

-- Node name is ':154' from file "digselector.tdf" line 36, column 44
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = LCELL( _EQ018);
  _EQ018 =  _LC1_C13
         #  _LC3_C13
         #  _LC4_C13;

-- Node name is '~157~1' from file "digselector.tdf" line 36, column 44
-- Equation name is '~157~1', location is LC5_C13, type is buried.
-- synthesized logic cell 
_LC5_C13 = LCELL( _EQ019);
  _EQ019 =  digin13 &  _LC5_A24
         #  digin23 &  _LC3_A24;

-- Node name is '~157~2' from file "digselector.tdf" line 36, column 44
-- Equation name is '~157~2', location is LC6_C13, type is buried.
-- synthesized logic cell 
_LC6_C13 = LCELL( _EQ020);
  _EQ020 =  digin33 &  _LC2_A24
         #  digin43 &  _LC1_A24;

-- Node name is '~157~3' from file "digselector.tdf" line 36, column 44
-- Equation name is '~157~3', location is LC8_C13, type is buried.
-- synthesized logic cell 
_LC8_C13 = LCELL( _EQ021);
  _EQ021 =  hour23 & !_LC8_A24
         #  hour13 & !_LC6_A24;

-- Node name is ':157' from file "digselector.tdf" line 36, column 44
-- Equation name is '_LC7_C13', type is buried 
_LC7_C13 = LCELL( _EQ022);
  _EQ022 =  _LC5_C13
         #  _LC6_C13
         #  _LC8_C13;



Project Information                                e:\4_monday\digselector.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,199K