main.rpt
来自「这个是个模拟红灯实验的」· RPT 代码 · 共 761 行 · 第 1/3 页
RPT
761 行
_LC3_A21~NOT = LCELL( _EQ014);
_EQ014 = !incount1 & incount2 & _LC6_A21;
-- Node name is ':258' from file "main.tdf" line 38, column 18
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = LCELL( _EQ015);
_EQ015 = _LC3_A15 & _LC6_A21
# _LC3_A15 & _LC8_A21;
-- Node name is '~322~1' from file "main.tdf" line 42, column 19
-- Equation name is '~322~1', location is LC4_A19, type is buried.
-- synthesized logic cell
_LC4_A19 = LCELL( _EQ016);
_EQ016 = _LC3_A19 & _LC7_A13
# incount1 & !incount2 & _LC7_A13;
-- Node name is '~322~2' from file "main.tdf" line 42, column 19
-- Equation name is '~322~2', location is LC1_A19, type is buried.
-- synthesized logic cell
_LC1_A19 = LCELL( _EQ017);
_EQ017 = _LC3_A19 & _LC4_A13
# _LC1_A15 & _LC4_A13
# _LC4_A19;
-- Node name is '~322~3' from file "main.tdf" line 42, column 19
-- Equation name is '~322~3', location is LC6_A13, type is buried.
-- synthesized logic cell
_LC6_A13 = LCELL( _EQ018);
_EQ018 = !incount2 & _LC5_A13;
-- Node name is ':322' from file "main.tdf" line 42, column 19
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ019);
_EQ019 = _LC1_A19
# _LC6_A13;
-- Node name is '~330~1' from file "main.tdf" line 43, column 1
-- Equation name is '~330~1', location is LC5_A13, type is buried.
-- synthesized logic cell
_LC5_A13 = LCELL( _EQ020);
_EQ020 = !incount3 & incount4;
-- Node name is '~353~1' from file "main.tdf" line 44, column 19
-- Equation name is '~353~1', location is LC2_A19, type is buried.
-- synthesized logic cell
_LC2_A19 = LCELL( _EQ021);
_EQ021 = !incount1 & incount2 & _LC4_A13
# !incount1 & incount2 & _LC7_A13;
-- Node name is '~353~2' from file "main.tdf" line 44, column 19
-- Equation name is '~353~2', location is LC2_A15, type is buried.
-- synthesized logic cell
_LC2_A15 = LCELL( _EQ022);
_EQ022 = !incount1 & incount2 & _LC1_A13
# !incount1 & incount2 & _LC3_A13;
-- Node name is '~353~3' from file "main.tdf" line 44, column 19
-- Equation name is '~353~3', location is LC6_A19, type is buried.
-- synthesized logic cell
_LC6_A19 = LCELL( _EQ023);
_EQ023 = _LC1_A13 & _LC3_A19
# _LC3_A13 & _LC3_A19
# _LC2_A15;
-- Node name is ':353' from file "main.tdf" line 44, column 19
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ024);
_EQ024 = _LC6_A19
# !_LC7_A19
# !_LC8_A19
# _LC2_A19;
-- Node name is '~362~1' from file "main.tdf" line 45, column 1
-- Equation name is '~362~1', location is LC1_A13, type is buried.
-- synthesized logic cell
_LC1_A13 = LCELL( _EQ025);
_EQ025 = !incount0 & _LC5_A13;
-- Node name is '~368~1' from file "main.tdf" line 45, column 19
-- Equation name is '~368~1', location is LC2_A21, type is buried.
-- synthesized logic cell
_LC2_A21 = LCELL( _EQ026);
_EQ026 = _LC1_A13
# incount1 & incount2 & _LC8_A21;
-- Node name is ':368' from file "main.tdf" line 45, column 19
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ027);
_EQ027 = _LC2_A21
# _LC4_A13;
-- Node name is '~378~1' from file "main.tdf" line 46, column 1
-- Equation name is '~378~1', location is LC3_A13, type is buried.
-- synthesized logic cell
_LC3_A13 = LCELL( _EQ028);
_EQ028 = incount0 & _LC5_A13;
-- Node name is '~380~1' from file "main.tdf" line 46, column 8
-- Equation name is '~380~1', location is LC5_A20, type is buried.
-- synthesized logic cell
_LC5_A20 = LCELL( _EQ029);
_EQ029 = _LC5_A21
# _LC3_A13 & _LC3_A15
# !_LC3_A21;
-- Node name is '~380~2' from file "main.tdf" line 46, column 8
-- Equation name is '~380~2', location is LC2_A13, type is buried.
-- synthesized logic cell
_LC2_A13 = LCELL( _EQ030);
_EQ030 = !incount1 & _LC5_A13
# !incount0 & _LC5_A13
# !incount2 & _LC5_A13;
-- Node name is ':380' from file "main.tdf" line 46, column 8
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = LCELL( _EQ031);
_EQ031 = _LC2_A13
# _LC1_A21
# _LC5_A20;
-- Node name is '~382~1' from file "main.tdf" line 46, column 12
-- Equation name is '~382~1', location is LC8_A20, type is buried.
-- synthesized logic cell
_LC8_A20 = LCELL( _EQ032);
_EQ032 = _LC1_A13 & _LC3_A15
# _LC2_A15
# _LC8_A13;
-- Node name is ':382' from file "main.tdf" line 46, column 12
-- Equation name is '_LC4_A20', type is buried
_LC4_A20 = LCELL( _EQ033);
_EQ033 = _LC3_A20
# _LC7_A21
# _LC8_A20
# _LC5_A20;
-- Node name is '~384~1' from file "main.tdf" line 46, column 26
-- Equation name is '~384~1', location is LC3_A20, type is buried.
-- synthesized logic cell
_LC3_A20 = LCELL( _EQ034);
_EQ034 = _LC2_A19
# _LC3_A15 & _LC7_A13
# _LC3_A15 & _LC4_A13;
-- Node name is '~384~2' from file "main.tdf" line 46, column 26
-- Equation name is '~384~2', location is LC6_A20, type is buried.
-- synthesized logic cell
_LC6_A20 = LCELL( _EQ035);
_EQ035 = _LC8_A13
# _LC2_A15
# _LC1_A13 & _LC3_A15;
-- Node name is ':384' from file "main.tdf" line 46, column 26
-- Equation name is '_LC2_A20', type is buried
_LC2_A20 = LCELL( _EQ036);
_EQ036 = _LC3_A20
# _LC7_A21
# _LC5_A20
# _LC6_A20;
Project Information e:\lon_4.7\4_try\4_what\main.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,950K
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