main.rpt
来自「这个是个模拟红灯实验的」· RPT 代码 · 共 761 行 · 第 1/3 页
RPT
761 行
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\lon_4.7\4_try\4_what\main.rpt
main
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 19 AND2 ! 0 2 0 1 :48
- 3 - A 19 AND2 s 2 0 0 5 ~59~1
- 8 - A 19 AND2 ! 0 2 0 1 :59
- 1 - A 15 AND2 s 2 0 0 1 ~74~1
- 4 - A 13 AND2 s 3 0 0 5 ~133~1
- 3 - A 15 AND2 s 2 0 0 5 ~133~2
- 7 - A 13 AND2 s 3 0 0 4 ~148~1
- 8 - A 21 AND2 s 1 1 0 3 ~159~1
- 6 - A 21 AND2 s 1 1 0 3 ~172~1
- 7 - A 21 OR2 2 2 1 3 :192
- 4 - A 21 AND2 s 2 0 0 3 ~210~1
- 1 - A 21 OR2 s 3 1 0 2 ~214~1
- 1 - A 20 OR2 0 4 1 0 :214
- 3 - A 21 AND2 ! 2 1 1 1 :221
- 5 - A 21 OR2 0 3 1 1 :258
- 4 - A 19 OR2 s 2 2 0 1 ~322~1
- 1 - A 19 OR2 s 0 4 0 2 ~322~2
- 6 - A 13 AND2 s 1 1 0 1 ~322~3
- 8 - A 13 OR2 0 2 1 2 :322
- 5 - A 13 AND2 s 2 0 0 4 ~330~1
- 2 - A 19 OR2 s 2 2 0 2 ~353~1
- 2 - A 15 OR2 s 2 2 0 3 ~353~2
- 6 - A 19 OR2 s 0 4 0 1 ~353~3
- 5 - A 19 OR2 0 4 1 0 :353
- 1 - A 13 AND2 s 1 1 0 5 ~362~1
- 2 - A 21 OR2 s 2 2 0 1 ~368~1
- 1 - A 14 OR2 0 2 1 0 :368
- 3 - A 13 AND2 s 1 1 0 3 ~378~1
- 5 - A 20 OR2 s 0 4 0 3 ~380~1
- 2 - A 13 OR2 s 3 1 0 1 ~380~2
- 7 - A 20 OR2 0 3 1 0 :380
- 8 - A 20 OR2 s 0 4 0 1 ~382~1
- 4 - A 20 OR2 0 4 1 0 :382
- 3 - A 20 OR2 s 0 4 0 3 ~384~1
- 6 - A 20 OR2 s 0 4 0 1 ~384~2
- 2 - A 20 OR2 0 4 1 0 :384
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\lon_4.7\4_try\4_what\main.rpt
main
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 0/ 48( 0%) 13/ 48( 27%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\lon_4.7\4_try\4_what\main.rpt
main
** EQUATIONS **
incount0 : INPUT;
incount1 : INPUT;
incount2 : INPUT;
incount3 : INPUT;
incount4 : INPUT;
-- Node name is 'DIGSELECT' from file "main.tdf" line 18, column 47
-- Equation name is 'DIGSELECT', type is output
DIGSELECT = _LC2_A20;
-- Node name is 'maingreen' from file "main.tdf" line 16, column 16
-- Equation name is 'maingreen', type is output
maingreen = _LC7_A20;
-- Node name is 'mainred' from file "main.tdf" line 16, column 27
-- Equation name is 'mainred', type is output
mainred = _LC1_A20;
-- Node name is 'mainyellow' from file "main.tdf" line 16, column 35
-- Equation name is 'mainyellow', type is output
mainyellow = _LC4_A20;
-- Node name is 'OUT10' from file "main.tdf" line 18, column 20
-- Equation name is 'OUT10', type is output
OUT10 = !_LC3_A21;
-- Node name is 'OUT11' from file "main.tdf" line 18, column 20
-- Equation name is 'OUT11', type is output
OUT11 = GND;
-- Node name is 'OUT12' from file "main.tdf" line 18, column 20
-- Equation name is 'OUT12', type is output
OUT12 = GND;
-- Node name is 'OUT13' from file "main.tdf" line 18, column 20
-- Equation name is 'OUT13', type is output
OUT13 = GND;
-- Node name is 'OUT20' from file "main.tdf" line 18, column 31
-- Equation name is 'OUT20', type is output
OUT20 = _LC1_A14;
-- Node name is 'OUT21' from file "main.tdf" line 18, column 31
-- Equation name is 'OUT21', type is output
OUT21 = _LC5_A19;
-- Node name is 'OUT22' from file "main.tdf" line 18, column 31
-- Equation name is 'OUT22', type is output
OUT22 = _LC8_A13;
-- Node name is 'OUT23' from file "main.tdf" line 18, column 31
-- Equation name is 'OUT23', type is output
OUT23 = _LC5_A21;
-- Node name is 'TRINGLE' from file "main.tdf" line 18, column 38
-- Equation name is 'TRINGLE', type is output
TRINGLE = _LC7_A21;
-- Node name is ':48' from file "main.tdf" line 20, column 1
-- Equation name is '_LC7_A19', type is buried
!_LC7_A19 = _LC7_A19~NOT;
_LC7_A19~NOT = LCELL( _EQ001);
_EQ001 = _LC3_A19 & _LC4_A13;
-- Node name is '~59~1' from file "main.tdf" line 21, column 1
-- Equation name is '~59~1', location is LC3_A19, type is buried.
-- synthesized logic cell
_LC3_A19 = LCELL( _EQ002);
_EQ002 = !incount1 & !incount2;
-- Node name is ':59' from file "main.tdf" line 21, column 1
-- Equation name is '_LC8_A19', type is buried
!_LC8_A19 = _LC8_A19~NOT;
_LC8_A19~NOT = LCELL( _EQ003);
_EQ003 = _LC3_A19 & _LC7_A13;
-- Node name is '~74~1' from file "main.tdf" line 22, column 1
-- Equation name is '~74~1', location is LC1_A15, type is buried.
-- synthesized logic cell
_LC1_A15 = LCELL( _EQ004);
_EQ004 = incount1 & !incount2;
-- Node name is '~133~1' from file "main.tdf" line 26, column 1
-- Equation name is '~133~1', location is LC4_A13, type is buried.
-- synthesized logic cell
_LC4_A13 = LCELL( _EQ005);
_EQ005 = !incount0 & !incount3 & !incount4;
-- Node name is '~133~2' from file "main.tdf" line 26, column 1
-- Equation name is '~133~2', location is LC3_A15, type is buried.
-- synthesized logic cell
_LC3_A15 = LCELL( _EQ006);
_EQ006 = incount1 & incount2;
-- Node name is '~148~1' from file "main.tdf" line 27, column 1
-- Equation name is '~148~1', location is LC7_A13, type is buried.
-- synthesized logic cell
_LC7_A13 = LCELL( _EQ007);
_EQ007 = incount0 & !incount3 & !incount4;
-- Node name is '~159~1' from file "main.tdf" line 29, column 1
-- Equation name is '~159~1', location is LC8_A21, type is buried.
-- synthesized logic cell
_LC8_A21 = LCELL( _EQ008);
_EQ008 = !incount0 & _LC4_A21;
-- Node name is '~172~1' from file "main.tdf" line 30, column 1
-- Equation name is '~172~1', location is LC6_A21, type is buried.
-- synthesized logic cell
_LC6_A21 = LCELL( _EQ009);
_EQ009 = incount0 & _LC4_A21;
-- Node name is ':192' from file "main.tdf" line 31, column 23
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = LCELL( _EQ010);
_EQ010 = !incount1 & !incount2 & _LC6_A21
# !incount2 & _LC8_A21;
-- Node name is '~210~1' from file "main.tdf" line 34, column 1
-- Equation name is '~210~1', location is LC4_A21, type is buried.
-- synthesized logic cell
_LC4_A21 = LCELL( _EQ011);
_EQ011 = incount3 & !incount4;
-- Node name is '~214~1' from file "main.tdf" line 34, column 9
-- Equation name is '~214~1', location is LC1_A21, type is buried.
-- synthesized logic cell
_LC1_A21 = LCELL( _EQ012);
_EQ012 = incount0 & incount1 & !incount2 & _LC4_A21
# !incount0 & !incount1 & incount2 & _LC4_A21;
-- Node name is ':214' from file "main.tdf" line 34, column 9
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = LCELL( _EQ013);
_EQ013 = _LC1_A21
# _LC1_A19
# _LC3_A20
# _LC7_A21;
-- Node name is ':221' from file "main.tdf" line 36, column 1
-- Equation name is '_LC3_A21', type is buried
!_LC3_A21 = _LC3_A21~NOT;
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