📄 8segment.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\lon_4.7\4_cross lights\8segment.rpt
8segment
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/144( 0%) 0/ 72( 0%) 7/ 72( 9%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\lon_4.7\4_cross lights\8segment.rpt
8segment
** EQUATIONS **
i0 : INPUT;
i1 : INPUT;
i2 : INPUT;
i3 : INPUT;
-- Node name is 'a' from file "8segment.tdf" line 9, column 13
-- Equation name is 'a', type is output
a = _LC4_C19;
-- Node name is 'b' from file "8segment.tdf" line 9, column 15
-- Equation name is 'b', type is output
b = _LC1_C32;
-- Node name is 'c' from file "8segment.tdf" line 9, column 17
-- Equation name is 'c', type is output
c = !_LC2_C32;
-- Node name is 'd' from file "8segment.tdf" line 9, column 19
-- Equation name is 'd', type is output
d = _LC7_C19;
-- Node name is 'e' from file "8segment.tdf" line 9, column 21
-- Equation name is 'e', type is output
e = _LC6_C19;
-- Node name is 'f' from file "8segment.tdf" line 9, column 23
-- Equation name is 'f', type is output
f = _LC4_C32;
-- Node name is 'g' from file "8segment.tdf" line 9, column 25
-- Equation name is 'g', type is output
g = _LC3_C19;
-- Node name is '~55~1' from file "8segment.tdf" line 12, column 1
-- Equation name is '~55~1', location is LC2_C19, type is buried.
-- synthesized logic cell
_LC2_C19 = LCELL( _EQ001);
_EQ001 = !i2 & !i3;
-- Node name is ':55' from file "8segment.tdf" line 12, column 1
-- Equation name is '_LC2_C32', type is buried
!_LC2_C32 = _LC2_C32~NOT;
_LC2_C32~NOT = LCELL( _EQ002);
_EQ002 = !i0 & i1 & !i2 & !i3;
-- Node name is ':63' from file "8segment.tdf" line 13, column 1
-- Equation name is '_LC3_C32', type is buried
!_LC3_C32 = _LC3_C32~NOT;
_LC3_C32~NOT = LCELL( _EQ003);
_EQ003 = i0 & i1 & !i2 & !i3;
-- Node name is ':73' from file "8segment.tdf" line 14, column 7
-- Equation name is '_LC4_C19', type is buried
_LC4_C19 = LCELL( _EQ004);
_EQ004 = !i0 & !i1 & i2 & !i3
# i0 & !i1 & !i2 & !i3;
-- Node name is '~90~1' from file "8segment.tdf" line 16, column 1
-- Equation name is '~90~1', location is LC5_C19, type is buried.
-- synthesized logic cell
_LC5_C19 = LCELL( _EQ005);
_EQ005 = i2 & !i3;
-- Node name is ':92' from file "8segment.tdf" line 16, column 9
-- Equation name is '_LC1_C32', type is buried
_LC1_C32 = LCELL( _EQ006);
_EQ006 = !i0 & i1 & i2 & !i3
# i0 & !i1 & i2 & !i3;
-- Node name is ':100' from file "8segment.tdf" line 17, column 13
-- Equation name is '_LC7_C19', type is buried
_LC7_C19 = LCELL( _EQ007);
_EQ007 = _LC4_C19
# i0 & i1 & _LC5_C19;
-- Node name is ':104' from file "8segment.tdf" line 17, column 17
-- Equation name is '_LC4_C32', type is buried
_LC4_C32 = LCELL( _EQ008);
_EQ008 = !_LC2_C32
# !_LC3_C32
# _LC1_C19;
-- Node name is '~106~1' from file "8segment.tdf" line 17, column 19
-- Equation name is '~106~1', location is LC1_C19, type is buried.
-- synthesized logic cell
_LC1_C19 = LCELL( _EQ009);
_EQ009 = i0 & !i1 & !i2 & !i3
# i0 & i1 & i2 & !i3;
-- Node name is ':106' from file "8segment.tdf" line 17, column 19
-- Equation name is '_LC3_C19', type is buried
_LC3_C19 = LCELL( _EQ010);
_EQ010 = _LC1_C19
# !i0 & !i1 & _LC2_C19;
-- Node name is '~117~1' from file "8segment.tdf" line 19, column 15
-- Equation name is '~117~1', location is LC8_C19, type is buried.
-- synthesized logic cell
_LC8_C19 = LCELL( _EQ011);
_EQ011 = i0 & !i1 & i2 & !i3
# i0 & i1 & !i2 & !i3
# i0 & !i1 & !i2 & i3;
-- Node name is ':117' from file "8segment.tdf" line 19, column 15
-- Equation name is '_LC6_C19', type is buried
_LC6_C19 = LCELL( _EQ012);
_EQ012 = _LC7_C19
# _LC8_C19;
Project Information e:\lon_4.7\4_cross lights\8segment.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,873K
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