mydisp.rpt

这个是个模拟红灯实验的

-- Node name is 'COLred23' 
-- Equation name is 'COLred23', type is output 
 COLred23 = LCELL( GND $  VCC);

-- Node name is 'COLred24' 
-- Equation name is 'COLred24', type is output 
 COLred24 = LCELL( GND $  VCC);

-- Node name is 'COLred25' 
-- Equation name is 'COLred25', type is output 
 COLred25 = LCELL( GND $  VCC);

-- Node name is 'COLred26' 
-- Equation name is 'COLred26', type is output 
 COLred26 = LCELL( GND $  VCC);

-- Node name is 'COLred27' 
-- Equation name is 'COLred27', type is output 
 COLred27 = LCELL( _EQ011 $ !INPUTCLK2);
  _EQ011 = !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred28' 
-- Equation name is 'COLred28', type is output 
 COLred28 = LCELL( _EQ012 $ !INPUTCLK2);
  _EQ012 = !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred29' 
-- Equation name is 'COLred29', type is output 
 COLred29 = LCELL( GND $  VCC);

-- Node name is 'COLred31' 
-- Equation name is 'COLred31', type is output 
 COLred31 = LCELL( GND $  VCC);

-- Node name is 'COLred32' 
-- Equation name is 'COLred32', type is output 
 COLred32 = LCELL( GND $  VCC);

-- Node name is 'COLred33' 
-- Equation name is 'COLred33', type is output 
 COLred33 = LCELL( GND $  VCC);

-- Node name is 'COLred34' 
-- Equation name is 'COLred34', type is output 
 COLred34 = LCELL( GND $  VCC);

-- Node name is 'COLred35' 
-- Equation name is 'COLred35', type is output 
 COLred35 = LCELL( GND $  VCC);

-- Node name is 'COLred36' 
-- Equation name is 'COLred36', type is output 
 COLred36 = LCELL( GND $  VCC);

-- Node name is 'COLred37' 
-- Equation name is 'COLred37', type is output 
 COLred37 = LCELL( GND $  VCC);

-- Node name is 'COLred38' 
-- Equation name is 'COLred38', type is output 
 COLred38 = LCELL( GND $  VCC);

-- Node name is 'COLred39' 
-- Equation name is 'COLred39', type is output 
 COLred39 = LCELL( GND $  VCC);

-- Node name is 'COLred41' 
-- Equation name is 'COLred41', type is output 
 COLred41 = LCELL( GND $  VCC);

-- Node name is 'COLred42' 
-- Equation name is 'COLred42', type is output 
 COLred42 = LCELL( GND $  VCC);

-- Node name is 'COLred43' 
-- Equation name is 'COLred43', type is output 
 COLred43 = LCELL( GND $  VCC);

-- Node name is 'COLred44' 
-- Equation name is 'COLred44', type is output 
 COLred44 = LCELL( GND $  VCC);

-- Node name is 'COLred45' 
-- Equation name is 'COLred45', type is output 
 COLred45 = LCELL( GND $  VCC);

-- Node name is 'COLred46' 
-- Equation name is 'COLred46', type is output 
 COLred46 = LCELL( GND $  VCC);

-- Node name is 'COLred47' 
-- Equation name is 'COLred47', type is output 
 COLred47 = LCELL( _EQ013 $  VCC);
  _EQ013 =  INPUTCLK0 &  INPUTCLK1 & !INPUTCLK2
         # !INPUTCLK0 & !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred48' 
-- Equation name is 'COLred48', type is output 
 COLred48 = LCELL( _EQ014 $  VCC);
  _EQ014 =  INPUTCLK0 &  INPUTCLK1 & !INPUTCLK2
         # !INPUTCLK0 & !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred49' 
-- Equation name is 'COLred49', type is output 
 COLred49 = LCELL( GND $  VCC);

-- Node name is 'COLred110' 
-- Equation name is 'COLred110', type is output 
 COLred110 = LCELL( GND $  VCC);

-- Node name is 'COLred111' 
-- Equation name is 'COLred111', type is output 
 COLred111 = LCELL( GND $  VCC);

-- Node name is 'COLred112' 
-- Equation name is 'COLred112', type is output 
 COLred112 = LCELL( GND $  VCC);

-- Node name is 'COLred113' 
-- Equation name is 'COLred113', type is output 
 COLred113 = LCELL( GND $  VCC);

-- Node name is 'COLred114' 
-- Equation name is 'COLred114', type is output 
 COLred114 = LCELL( GND $  VCC);

-- Node name is 'COLred115' 
-- Equation name is 'COLred115', type is output 
 COLred115 = LCELL( GND $  VCC);

-- Node name is 'COLred116' 
-- Equation name is 'COLred116', type is output 
 COLred116 = LCELL( GND $  VCC);

-- Node name is 'COLred210' 
-- Equation name is 'COLred210', type is output 
 COLred210 = LCELL( GND $  VCC);

-- Node name is 'COLred211' 
-- Equation name is 'COLred211', type is output 
 COLred211 = LCELL( GND $  VCC);

-- Node name is 'COLred212' 
-- Equation name is 'COLred212', type is output 
 COLred212 = LCELL( GND $  VCC);

-- Node name is 'COLred213' 
-- Equation name is 'COLred213', type is output 
 COLred213 = LCELL( GND $  VCC);

-- Node name is 'COLred214' 
-- Equation name is 'COLred214', type is output 
 COLred214 = LCELL( GND $  VCC);

-- Node name is 'COLred215' 
-- Equation name is 'COLred215', type is output 
 COLred215 = LCELL( _EQ015 $  VCC);
  _EQ015 =  INPUTCLK0 &  INPUTCLK1 & !INPUTCLK2
         # !INPUTCLK0 & !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred216' 
-- Equation name is 'COLred216', type is output 
 COLred216 = LCELL( _EQ016 $  VCC);
  _EQ016 =  INPUTCLK0 &  INPUTCLK1 & !INPUTCLK2
         # !INPUTCLK0 & !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred310' 
-- Equation name is 'COLred310', type is output 
 COLred310 = LCELL( GND $  VCC);

-- Node name is 'COLred311' 
-- Equation name is 'COLred311', type is output 
 COLred311 = LCELL( GND $  VCC);

-- Node name is 'COLred312' 
-- Equation name is 'COLred312', type is output 
 COLred312 = LCELL( GND $  VCC);

-- Node name is 'COLred313' 
-- Equation name is 'COLred313', type is output 
 COLred313 = LCELL( GND $  VCC);

-- Node name is 'COLred314' 
-- Equation name is 'COLred314', type is output 
 COLred314 = LCELL( GND $  VCC);

-- Node name is 'COLred315' 
-- Equation name is 'COLred315', type is output 
 COLred315 = LCELL( _EQ017 $ !INPUTCLK2);
  _EQ017 = !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred316' 
-- Equation name is 'COLred316', type is output 
 COLred316 = LCELL( _EQ018 $ !INPUTCLK2);
  _EQ018 = !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred410' 
-- Equation name is 'COLred410', type is output 
 COLred410 = LCELL( GND $  VCC);

-- Node name is 'COLred411' 
-- Equation name is 'COLred411', type is output 
 COLred411 = LCELL( GND $  VCC);

-- Node name is 'COLred412' 
-- Equation name is 'COLred412', type is output 
 COLred412 = LCELL( GND $  VCC);

-- Node name is 'COLred413' 
-- Equation name is 'COLred413', type is output 
 COLred413 = LCELL( GND $  VCC);

-- Node name is 'COLred414' 
-- Equation name is 'COLred414', type is output 
 COLred414 = LCELL( GND $  VCC);

-- Node name is 'COLred415' 
-- Equation name is 'COLred415', type is output 
 COLred415 = LCELL( _EQ019 $ !INPUTCLK2);
  _EQ019 = !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'COLred416' 
-- Equation name is 'COLred416', type is output 
 COLred416 = LCELL( _EQ020 $ !INPUTCLK2);
  _EQ020 = !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'ROW1' 
-- Equation name is 'ROW1', type is output 
 ROW1    = LCELL( _EQ021 $  GND);
  _EQ021 = !INPUTCLK0 & !INPUTCLK1 & !INPUTCLK2;

-- Node name is 'ROW2' 
-- Equation name is 'ROW2', type is output 
 ROW2    = LCELL( _EQ022 $  GND);
  _EQ022 =  INPUTCLK0 & !INPUTCLK1 & !INPUTCLK2;

-- Node name is 'ROW3' 
-- Equation name is 'ROW3', type is output 
 ROW3    = LCELL( _EQ023 $  GND);
  _EQ023 = !INPUTCLK0 &  INPUTCLK1 & !INPUTCLK2;

-- Node name is 'ROW4' 
-- Equation name is 'ROW4', type is output 
 ROW4    = LCELL( _EQ024 $  GND);
  _EQ024 =  INPUTCLK0 &  INPUTCLK1 & !INPUTCLK2;

-- Node name is 'ROW5' 
-- Equation name is 'ROW5', type is output 
 ROW5    = LCELL( _EQ025 $  GND);
  _EQ025 = !INPUTCLK0 & !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'ROW6' 
-- Equation name is 'ROW6', type is output 
 ROW6    = LCELL( _EQ026 $  GND);
  _EQ026 =  INPUTCLK0 & !INPUTCLK1 &  INPUTCLK2;

-- Node name is 'ROW7' 
-- Equation name is 'ROW7', type is output 
 ROW7    = LCELL( _EQ027 $  GND);
  _EQ027 = !INPUTCLK0 &  INPUTCLK1 &  INPUTCLK2;

-- Node name is 'ROW8' 
-- Equation name is 'ROW8', type is output 
 ROW8    = LCELL( _EQ028 $  GND);
  _EQ028 =  INPUTCLK0 &  INPUTCLK1 &  INPUTCLK2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                   e:\lon\4_what\mydisp.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,414K