📄 mydisp.rpt
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Project Information e:\lon\4_what\mydisp.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/09/2006 16:31:03
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was unsuccessful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mydisp EPM7096QC100-7 3 136 0 136 0 No Fit
User Pins: 3 136 0
Project Information e:\lon\4_what\mydisp.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'COLgre114' is stuck at VCC
Warning: Primitive 'COLgre113' is stuck at VCC
Warning: Primitive 'COLgre112' is stuck at VCC
Warning: Primitive 'COLgre111' is stuck at VCC
Warning: Primitive 'COLgre110' is stuck at VCC
Warning: Primitive 'COLgre19' is stuck at VCC
Warning: Primitive 'COLgre18' is stuck at VCC
Warning: Primitive 'COLgre17' is stuck at VCC
Warning: Primitive 'COLgre16' is stuck at VCC
Warning: Primitive 'COLgre15' is stuck at VCC
Warning: Primitive 'COLgre14' is stuck at VCC
Warning: Primitive 'COLgre13' is stuck at VCC
Warning: Primitive 'COLgre12' is stuck at VCC
Warning: Primitive 'COLgre11' is stuck at VCC
Warning: Primitive 'COLgre214' is stuck at VCC
Warning: Primitive 'COLgre213' is stuck at VCC
Warning: Primitive 'COLgre212' is stuck at VCC
Warning: Primitive 'COLgre211' is stuck at VCC
Warning: Primitive 'COLgre210' is stuck at VCC
Warning: Primitive 'COLgre29' is stuck at VCC
Warning: Primitive 'COLgre28' is stuck at VCC
Warning: Primitive 'COLgre27' is stuck at VCC
Warning: Primitive 'COLgre26' is stuck at VCC
Warning: Primitive 'COLgre25' is stuck at VCC
Warning: Primitive 'COLgre24' is stuck at VCC
Warning: Primitive 'COLgre23' is stuck at VCC
Warning: Primitive 'COLgre22' is stuck at VCC
Warning: Primitive 'COLgre21' is stuck at VCC
Warning: Primitive 'COLgre316' is stuck at VCC
Warning: Primitive 'COLgre315' is stuck at VCC
Warning: Primitive 'COLgre314' is stuck at VCC
Warning: Primitive 'COLgre313' is stuck at VCC
Warning: Primitive 'COLgre312' is stuck at VCC
Warning: Primitive 'COLgre311' is stuck at VCC
Warning: Primitive 'COLgre310' is stuck at VCC
Warning: Primitive 'COLgre39' is stuck at VCC
Warning: Primitive 'COLgre36' is stuck at VCC
Warning: Primitive 'COLgre35' is stuck at VCC
Warning: Primitive 'COLgre34' is stuck at VCC
Warning: Primitive 'COLgre33' is stuck at VCC
Warning: Primitive 'COLgre32' is stuck at VCC
Warning: Primitive 'COLgre31' is stuck at VCC
Warning: Primitive 'COLgre416' is stuck at VCC
Warning: Primitive 'COLgre415' is stuck at VCC
Warning: Primitive 'COLgre414' is stuck at VCC
Warning: Primitive 'COLgre413' is stuck at VCC
Warning: Primitive 'COLgre412' is stuck at VCC
Warning: Primitive 'COLgre411' is stuck at VCC
Warning: Primitive 'COLgre410' is stuck at VCC
Warning: Primitive 'COLgre49' is stuck at VCC
Warning: Primitive 'COLgre46' is stuck at VCC
Warning: Primitive 'COLgre45' is stuck at VCC
Warning: Primitive 'COLgre44' is stuck at VCC
Warning: Primitive 'COLgre43' is stuck at VCC
Warning: Primitive 'COLgre42' is stuck at VCC
Warning: Primitive 'COLgre41' is stuck at VCC
Warning: Primitive 'COLred116' is stuck at VCC
Warning: Primitive 'COLred115' is stuck at VCC
Warning: Primitive 'COLred114' is stuck at VCC
Warning: Primitive 'COLred113' is stuck at VCC
Warning: Primitive 'COLred112' is stuck at VCC
Warning: Primitive 'COLred111' is stuck at VCC
Warning: Primitive 'COLred110' is stuck at VCC
Warning: Primitive 'COLred19' is stuck at VCC
Warning: Primitive 'COLred16' is stuck at VCC
Warning: Primitive 'COLred15' is stuck at VCC
Warning: Primitive 'COLred14' is stuck at VCC
Warning: Primitive 'COLred13' is stuck at VCC
Warning: Primitive 'COLred12' is stuck at VCC
Warning: Primitive 'COLred11' is stuck at VCC
Warning: Primitive 'COLred214' is stuck at VCC
Warning: Primitive 'COLred213' is stuck at VCC
Warning: Primitive 'COLred212' is stuck at VCC
Warning: Primitive 'COLred211' is stuck at VCC
Warning: Primitive 'COLred210' is stuck at VCC
Warning: Primitive 'COLred29' is stuck at VCC
Warning: Primitive 'COLred26' is stuck at VCC
Warning: Primitive 'COLred25' is stuck at VCC
Warning: Primitive 'COLred24' is stuck at VCC
Warning: Primitive 'COLred23' is stuck at VCC
Warning: Primitive 'COLred22' is stuck at VCC
Warning: Primitive 'COLred21' is stuck at VCC
Warning: Primitive 'COLred314' is stuck at VCC
Warning: Primitive 'COLred313' is stuck at VCC
Warning: Primitive 'COLred312' is stuck at VCC
Warning: Primitive 'COLred311' is stuck at VCC
Warning: Primitive 'COLred310' is stuck at VCC
Warning: Primitive 'COLred39' is stuck at VCC
Warning: Primitive 'COLred38' is stuck at VCC
Warning: Primitive 'COLred37' is stuck at VCC
Warning: Primitive 'COLred36' is stuck at VCC
Warning: Primitive 'COLred35' is stuck at VCC
Warning: Primitive 'COLred34' is stuck at VCC
Warning: Primitive 'COLred33' is stuck at VCC
Warning: Primitive 'COLred32' is stuck at VCC
Warning: Primitive 'COLred31' is stuck at VCC
Warning: Primitive 'COLred414' is stuck at VCC
Warning: Primitive 'COLred413' is stuck at VCC
Warning: Primitive 'COLred412' is stuck at VCC
Warning: Primitive 'COLred411' is stuck at VCC
Warning: Primitive 'COLred410' is stuck at VCC
Warning: Primitive 'COLred49' is stuck at VCC
Warning: Primitive 'COLred46' is stuck at VCC
Warning: Primitive 'COLred45' is stuck at VCC
Warning: Primitive 'COLred44' is stuck at VCC
Warning: Primitive 'COLred43' is stuck at VCC
Warning: Primitive 'COLred42' is stuck at VCC
Warning: Primitive 'COLred41' is stuck at VCC
Error: Project does not fit in specified device(s)
Error: No fit found, generating Report File
(See individual chip error summaries for additional information)
Device-Specific Information: e:\lon\4_what\mydisp.rpt
mydisp
***** Logic for device 'mydisp' contains errors -- see ERROR SUMMARY.
Device: EPM7096QC100-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: e:\lon\4_what\mydisp.rpt
mydisp
** ERROR SUMMARY **
Error: Project requires too many (136/72) output pins
Error: Project requires too many (136/96) logic cells
Device-Specific Information: e:\lon\4_what\mydisp.rpt
mydisp
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 0/72 ( 0%)
Total logic cells used: 0/96 ( 0%)
Total shareable expanders used: 0/96 ( 0%)
Total Turbo logic cells used: 136/96 (141%)
Total shareable expanders not available (n/a): 0/96 ( 0%)
Average fan-in: 0.52
Total fan-in: 72
Total input pins required: 3
Total output pins required: 136
Total bidirectional pins required: 0
Total logic cells required: 136
Total flipflops required: 0
Total product terms required: 156
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 96 ( 0%)
Device-Specific Information: e:\lon\4_what\mydisp.rpt
mydisp
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
?? - ?? INPUT 0 0 0 0 0 16 0 INPUTCLK0
?? - ?? INPUT 0 0 0 0 0 28 0 INPUTCLK1
?? - ?? INPUT 0 0 0 0 0 28 0 INPUTCLK2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\lon\4_what\mydisp.rpt
mydisp
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre11
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre12
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre13
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre14
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre15
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre16
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre17
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre18
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre19
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre21
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre22
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre23
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre24
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre25
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre26
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre27
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre28
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre29
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre31
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre32
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre33
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre34
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre35
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre36
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLgre37
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLgre38
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre39
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre41
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre42
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre43
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre44
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre45
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre46
?? ?? ?? OUTPUT t 0 0 0 3 0 0 0 COLgre47
?? ?? ?? OUTPUT t 0 0 0 3 0 0 0 COLgre48
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre49
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre110
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre111
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre112
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre113
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre114
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLgre115
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLgre116
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre210
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre211
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre212
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre213
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre214
?? ?? ?? OUTPUT t 0 0 0 3 0 0 0 COLgre215
?? ?? ?? OUTPUT t 0 0 0 3 0 0 0 COLgre216
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre310
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre311
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre312
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre313
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre314
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre315
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre316
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre410
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre411
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre412
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre413
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre414
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre415
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLgre416
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred11
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred12
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred13
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred14
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred15
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred16
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLred17
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLred18
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred19
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred21
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred22
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred23
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred24
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred25
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred26
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLred27
?? ?? ?? OUTPUT t 0 0 0 2 0 0 0 COLred28
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred29
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred31
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred32
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred33
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred34
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred35
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred36
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred37
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred38
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred39
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred41
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred42
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred43
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred44
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred45
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred46
?? ?? ?? OUTPUT t 0 0 0 3 0 0 0 COLred47
?? ?? ?? OUTPUT t 0 0 0 3 0 0 0 COLred48
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred49
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred110
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred111
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred112
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred113
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred114
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred115
?? ?? ?? OUTPUT t 0 0 0 0 0 0 0 COLred116
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