📄 myexpand.rpt
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Project Information e:\4_monday\myexpand.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/10/2006 19:47:36
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
myexpand EPM7064LC68-7 9 40 0 40 15 62 %
User Pins: 9 40 0
Device-Specific Information: e:\4_monday\myexpand.rpt
myexpand
***** Logic for device 'myexpand' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: e:\4_monday\myexpand.rpt
myexpand
** ERROR SUMMARY **
Info: Chip 'myexpand' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
d d d N
I I a a a I d d
N N t t t G a a
P P a a a H t t
U U o o o V T a a
T T u u u C _ o o V
C C t t t C M u u C R R
L L 1 G 1 1 I G G G O G t t C O O
K K 1 N 1 1 N N N N D N 0 0 I W W
0 1 1 D 2 3 T D D D E D 7 8 O 1 2
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
incount0 | 10 60 | ROW3
VCCIO | 11 59 | ROW4
incount1 | 12 58 | GND
incount2 | 13 57 | ROW5
INPUTCLK2 | 14 56 | ROW6
incount3 | 15 55 | dataout015
GND | 16 54 | dataout016
incount4 | 17 53 | VCCIO
dataout114 | 18 EPM7064LC68-7 52 | dataout17
dataout12 | 19 51 | dataout18
dataout011 | 20 50 | dataout09
VCCIO | 21 49 | dataout010
dataout012 | 22 48 | GND
dataout15 | 23 47 | dataout02
dataout11 | 24 46 | dataout06
dataout14 | 25 45 | dataout03
GND | 26 44 | dataout05
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
d d d d V d d G V d R G R d d d V
a a a a C a a N C a O N O a a a C
t t t t C t t D C t W D W t t t C
a a a a I a a I a 8 7 a a a I
o o o o O o o N o o o o O
u u u u u u T u u u u
t t t t t t t t t t
0 1 1 0 1 1 0 1 1 0
1 6 3 1 1 9 1 1 1 4
4 3 0 6 5
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\4_monday\myexpand.rpt
myexpand
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 4/16( 25%) 12/12(100%) 0/16( 0%) 3/36( 8%)
B: LC17 - LC32 12/16( 75%) 12/12(100%) 0/16( 0%) 3/36( 8%)
C: LC33 - LC48 12/16( 75%) 12/12(100%) 8/16( 50%) 9/36( 25%)
D: LC49 - LC64 12/16( 75%) 12/12(100%) 15/16( 93%) 9/36( 25%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 48/48 (100%)
Total logic cells used: 40/64 ( 62%)
Total shareable expanders used: 15/64 ( 23%)
Total Turbo logic cells used: 40/64 ( 62%)
Total shareable expanders not available (n/a): 8/64 ( 12%)
Average fan-in: 4.80
Total fan-in: 192
Total input pins required: 9
Total output pins required: 40
Total bidirectional pins required: 0
Total logic cells required: 40
Total flipflops required: 0
Total product terms required: 103
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: e:\4_monday\myexpand.rpt
myexpand
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
10 (9) (A) INPUT 0 0 0 0 0 8 0 incount0
12 (8) (A) INPUT 0 0 0 0 0 8 0 incount1
13 (6) (A) INPUT 0 0 0 0 0 8 0 incount2
15 (4) (A) INPUT 0 0 0 0 0 40 0 incount3
17 (3) (A) INPUT 0 0 0 0 0 40 0 incount4
9 (11) (A) INPUT 0 0 0 0 0 16 0 INPUTCLK0
8 (12) (A) INPUT 0 0 0 0 0 16 0 INPUTCLK1
14 (5) (A) INPUT 0 0 0 0 0 16 0 INPUTCLK2
67 - - INPUT 0 0 0 0 0 40 0 NIGHT_MODE
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\4_monday\myexpand.rpt
myexpand
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
36 33 C OUTPUT t 0 0 0 3 0 0 0 dataout01
47 45 C OUTPUT t 0 0 0 3 0 0 0 dataout02
45 43 C OUTPUT t 0 0 0 3 0 0 0 dataout03
42 40 C OUTPUT t 0 0 0 3 0 0 0 dataout04
44 41 C OUTPUT t 0 0 0 3 0 0 0 dataout05
46 44 C OUTPUT t 0 0 0 3 0 0 0 dataout06
65 64 D OUTPUT t 6 5 1 9 0 0 0 dataout07
64 62 D OUTPUT t 6 5 1 9 0 0 0 dataout08
50 48 C OUTPUT t 0 0 0 3 0 0 0 dataout09
49 46 C OUTPUT t 0 0 0 3 0 0 0 dataout010
20 30 B OUTPUT t 0 0 0 3 0 0 0 dataout011
24 27 B OUTPUT t 0 0 0 3 0 0 0 dataout11
22 29 B OUTPUT t 0 0 0 3 0 0 0 dataout012
19 32 B OUTPUT t 0 0 0 3 0 0 0 dataout12
30 20 B OUTPUT t 0 0 0 3 0 0 0 dataout013
29 21 B OUTPUT t 0 0 0 3 0 0 0 dataout13
27 24 B OUTPUT t 0 0 0 3 0 0 0 dataout014
25 25 B OUTPUT t 0 0 0 3 0 0 0 dataout14
55 53 D OUTPUT t 7 6 1 9 0 0 0 dataout015
23 28 B OUTPUT t 0 0 0 3 0 0 0 dataout15
54 52 D OUTPUT t 7 6 1 9 0 0 0 dataout016
28 22 B OUTPUT t 0 0 0 3 0 0 0 dataout16
52 51 D OUTPUT t 5 4 1 9 0 0 0 dataout17
51 49 D OUTPUT t 5 4 1 9 0 0 0 dataout18
33 17 B OUTPUT t 0 0 0 3 0 0 0 dataout19
32 19 B OUTPUT t 0 0 0 3 0 0 0 dataout110
7 13 A OUTPUT t 0 0 0 3 0 0 0 dataout111
5 14 A OUTPUT t 0 0 0 3 0 0 0 dataout112
4 16 A OUTPUT t 0 0 0 3 0 0 0 dataout113
18 1 A OUTPUT t 0 0 0 3 0 0 0 dataout114
41 38 C OUTPUT t 7 6 1 9 0 0 0 dataout115
40 37 C OUTPUT t 7 6 1 9 0 0 0 dataout116
62 61 D OUTPUT t 0 0 0 6 0 0 0 ROW1
61 60 D OUTPUT t 0 0 0 6 0 0 0 ROW2
60 59 D OUTPUT t 0 0 0 6 0 0 0 ROW3
59 57 D OUTPUT t 0 0 0 6 0 0 0 ROW4
57 56 D OUTPUT t 0 0 0 6 0 0 0 ROW5
56 54 D OUTPUT t 0 0 0 6 0 0 0 ROW6
39 36 C OUTPUT t 0 0 0 6 0 0 0 ROW7
37 35 C OUTPUT t 0 0 0 6 0 0 0 ROW8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\4_monday\myexpand.rpt
myexpand
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------- LC13 dataout111
| +----- LC14 dataout112
| | +--- LC16 dataout113
| | | +- LC1 dataout114
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'A'
LC | | | | | A B C D | Logic cells that feed LAB 'A':
Pin
15 -> * * * * | * * * * | <-- incount3
17 -> * * * * | * * * * | <-- incount4
67 -> * * * * | * * * * | <-- NIGHT_MODE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\4_monday\myexpand.rpt
myexpand
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC30 dataout011
| +--------------------- LC27 dataout11
| | +------------------- LC29 dataout012
| | | +----------------- LC32 dataout12
| | | | +--------------- LC20 dataout013
| | | | | +------------- LC21 dataout13
| | | | | | +----------- LC24 dataout014
| | | | | | | +--------- LC25 dataout14
| | | | | | | | +------- LC28 dataout15
| | | | | | | | | +----- LC22 dataout16
| | | | | | | | | | +--- LC17 dataout19
| | | | | | | | | | | +- LC19 dataout110
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
15 -> * * * * * * * * * * * * | * * * * | <-- incount3
17 -> * * * * * * * * * * * * | * * * * | <-- incount4
67 -> * * * * * * * * * * * * | * * * * | <-- NIGHT_MODE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
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