fx2_to_extsyncfifo.c

CY7c68013 GPIF程序绝对可用

}

BOOL DR_GetStatus(void)
{
   return(TRUE);
}

BOOL DR_ClearFeature(void)
{
   return(TRUE);
}

BOOL DR_SetFeature(void)
{
   return(TRUE);
}


#define	VR_UPLOAD		0xc0
#define VR_DOWNLOAD		0x40
#define VR_CONFIGNUMB   0xB2
#define VR_RD_CONFIGNUMB 0xB3
#define VR_USRCMD       0xB4
#define VR_LEDON        0xB5
#define VR_LEDOFF       0xB6

BOOL DR_VendorCmnd(void)
{

  switch (SETUPDAT[1])
  {
       case VR_CONFIGNUMB:
	     *EP0BUF = VR_CONFIGNUMB;
         ConfigNumb=0;
          ConfigNumb=SETUPDAT[2];
          ConfigNumb<<=8;
          ConfigNumb|=SETUPDAT[3];
          if(ConfigNumb>0)
		 {   nCONFIG=0;
		     EZUSB_Delay(200);
             nCONFIG=1;
             EZUSB_Delay(400);
             if(nSTATUS)
		    {LEDIO=0;
		     EZUSB_Delay(400);
			 LEDIO=1;
             }
			else
             LEDIO=0;
            
		 }

          EP0BCH = 0;
	  	  EP0BCL = 1;
	      EP0CS |= bmHSNAK;
       break;
	   case VR_RD_CONFIGNUMB:
	     
	   	*(EP0BUF)= (BYTE)(ConfigNumb>>8);
       	*(EP0BUF+1)=(BYTE)(ConfigNumb);
        *(EP0BUF+2)= (BYTE)(RxdCounter>>8);
        *(EP0BUF+3)=(BYTE)(RxdCounter);
        *(EP0BUF+4)=rxd_len;
		*(EP0BUF+5)= TrigSite_H;
       	*(EP0BUF+6)=TrigSite_L;

          EP0BCH = 0;		
	  	  EP0BCL =7;
	      EP0CS |= bmHSNAK;
	      break;
	   case VR_LEDON:
	      *EP0BUF = VR_LEDON;
	      LEDIO=0;
	      nCONFIG=0;
	      EP0BCH = 0;
	  	  EP0BCL = 1;
	      EP0CS |= bmHSNAK;
		  break;

	   case VR_LEDOFF:
		    *EP0BUF = VR_LEDOFF;
			 nCONFIG=1;
	         LEDIO=1;
	         EP0BCH = 0;
	  	     EP0BCL = 1;
	         EP0CS |= bmHSNAK;
		  break;

         case VR_USRCMD:
		   rxd_len=SETUPDAT[2];
	  	 	if(SETUPDAT[0] == VR_DOWNLOAD)
			 {  	EP0BCH = 0;
					EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
	 		   while(EP0CS & bmEPBUSY);
			        if(*EP0BUF=='R'){
                  in_enable=1;
                  	}else
					 if(*EP0BUF=='P'){
                  in_enable=0;}

			        WriteCMD_GPIF(EP0BUF);
          
        
		 	}
         break;
   default:
        return(TRUE);
  }

  return(FALSE);
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{ 
   GotSUD = TRUE;            // Set flag
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUDAV;         // Clear SUDAV IRQ
  
}

// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUTOK;         // Clear SUTOK IRQ
}

void ISR_Sof(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSOF;            // Clear SOF IRQ
}

void ISR_Ures(void) interrupt 0
{
   // whenever we get a USB reset, we should revert to full speed mode
   pConfigDscr = pFullSpeedConfigDscr;
   ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
   pOtherConfigDscr = pHighSpeedConfigDscr;
   ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmURES;         // Clear URES IRQ
}

void ISR_Susp(void) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUSP;
}

void ISR_Highspeed(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
      pOtherConfigDscr = pFullSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
   	//	PA3=0;
	  }
else

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}


/*
void Setup_FLOWSTATE_Read ( void )
{
   FLOWSTATE = FlowStates[18];  // 1000 0011b - FSE=1, FS[2:0]=003
   SYNCDELAY;
   FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
   SYNCDELAY;
   FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
   SYNCDELAY;
}

void Setup_FLOWSTATE_Write ( void )
{ 
   FLOWSTATE = FlowStates[27];  // 1000 0001b - FSE=1, FS[2:0]=001
   SYNCDELAY;
   FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows)
   SYNCDELAY;
   FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow)
   SYNCDELAY;
}

void Delay(unsigned int n)
{
unsigned int i;
for(i=0;i<n;i++)
;
}
*/
void SendData(BYTE d)
{  BYTE i;
   DCLK=0;
  for(i=0;i<8;i++)
  {DATA0=(bit)(d&0x01);
   d>>=1;
   DCLK=1;
   DCLK=0;
  }
  
}

/*
void Clock(void)
{
Delay(10);
SK=1;
Delay(10);
SK=0;
}*/



 /* if( GPIFTRIG & 0x80 )               // if GPIF interface IDLE
  {   
    if ( ! ( EP24FIFOFLGS & 0x02 ) )  // if there's a packet in the peripheral domain for EP2
	{
      if ( EXTFIFONOTFULL )           // if the external FIFO is not full
	  {  
	    if(enum_high_speed)
		{
	      SYNCDELAY;    
          GPIFTCB1 = 0x02;            // setup transaction count (512 bytes/2 for word wide -> 0x0100)
          SYNCDELAY;
          GPIFTCB0 = 0x00;
          SYNCDELAY;
		}
		else
		{
		  SYNCDELAY;
		  GPIFTCB1 = 0x00;            // setup transaction count (64 bytes/2 for word wide -> 0x20)
          SYNCDELAY;
		  GPIFTCB0 = 0x40;
		  SYNCDELAY;
		}
	    Setup_FLOWSTATE_Write();      // setup FLOWSTATE registers for FIFO Write operation
        SYNCDELAY;
        GPIFTRIG = GPIF_EP2;          // launch GPIF FIFO WRITE Transaction from EP2 FIFO
        SYNCDELAY;
   
	    while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
        {
          ;
        }
        SYNCDELAY;
	  }
    }
  }
*/