📄 fx2_to_extsyncfifo.c
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//modfiy at 2005-1-7
//with fpga
#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File: FX2_to_extsyncFIFO.c
// Contents: Hooks required to implement FX2 GPIF to external sync. FIFO
// interface using CY4265-15AC
//
// Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
// Ref. Manual for usage details.
#define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1
#define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0
#define GPIFTRIGRD 4
#define GPIF_EP2 0
#define GPIF_EP4 1
#define GPIF_EP6 2
#define GPIF_EP8 3
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
BOOL in_enable = FALSE; // flag to enable IN transfers
BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
//sbit Enable = IOA ^ 0; //PIN 3
//sbit DO = IOA ^ 1; //PIN 6
//sbit SK = IOA ^ 2; //PIN 4
//sbit Rst= IOA^ 7;
sbit nSTATUS=IOA^7; //input
sbit CONFIG_DONE=IOA^6; //input
sbit nCONFIG=IOA^5; //out
sbit DCLK=IOA^4; //out
sbit DATA0=IOA^3; //out
sbit LEDIO=IOA^2;
sbit DEVICE_STATE=IOA^1; //in
sbit AD_IRQ =IOA^0;
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void Setup_FLOWSTATE_Write ( void );
void Setup_FLOWSTATE_Read ( void );
void GpifInit ();
void Delay(unsigned int n);
//void Clock(void);
void SendData(BYTE d);
WORD ConfigNumb;
WORD RxdCounter;
BYTE TrigSite_H,TrigSite_L;
BYTE cmd_buffer[8];
BYTE rxd_len;
static WORD xdata Tcount = 0; // transaction count
static WORD xFIFOBC_IN = 0x0000; // variable that contains EP6FIFOBCH/L value
void GPIF_SingleByteWrite (BYTE gdata)
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
XGPIFSGLDATLX = gdata; // trigger GPIF Single Byte Write transaction
}
void WriteCMD_GPIF(BYTE * buf)
{
BYTE i;
while(DEVICE_STATE);
for(i=0;i<rxd_len;i++)
GPIF_SingleByteWrite(*(buf+i));
LEDIO=0;
// EZUSB_Delay(50);
LEDIO=1;
}
void int0_isr (void) interrupt 0
{
EX0 = 0;
cmd_buffer[0]='P';
WriteCMD_GPIF(cmd_buffer);
in_enable = TRUE;
/*
LEDIO=0;
EZUSB_Delay(50);
LEDIO=1;
cmd_buffer[0]='R';
WriteCMD_GPIF(cmd_buffer);
LEDIO=0;
EZUSB_Delay(50);
LEDIO=1;
EX0 = 1; */
}
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
// set the slave FIFO interface to 48MHz
in_enable=0;
rxd_len=0;
cmd_buffer[0]=cmd_buffer[1]=cmd_buffer[2]=cmd_buffer[3]=cmd_buffer[4]=cmd_buffer[5]=cmd_buffer[6]=cmd_buffer[7]=0;
REVCTL = 0x02; // REVCTL.1=1; use "dynamic OUT automaticity"
EP1INCFG = 0x00; // always not valid, bulk
SYNCDELAY;
EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
SYNCDELAY;
EP4CFG = 0x00; // EP4 not valid
SYNCDELAY;
EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
SYNCDELAY;
EP8CFG = 0x00; // EP8 not valid
SYNCDELAY;
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x02; // reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit
SYNCDELAY;
//EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, byte ops
SYNCDELAY;
EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6AUTOINLENH=0x02;
SYNCDELAY;
EP6AUTOINLENL=0x00;
SYNCDELAY;
GpifInit (); // initialize GPIF registers
TrigSite_H=0x12;
TrigSite_L=0x34;
ConfigNumb=0;
RxdCounter=0;
OEA=0xFF;
OEA=0xFF;
nSTATUS=1;
CONFIG_DONE=1;
nCONFIG=1;
DCLK=1;
DATA0=1;
LEDIO=0;
EZUSB_Delay(10);
LEDIO=1;
EZUSB_Delay(10);
}
#define HPI_RDY GPIFREADYSTAT & bmBIT0 // RDY0
void TD_Poll(void)
{ // WORD i;
// WORD count;
/*
if(!(EP2468STAT & bmEP2EMPTY))
{ // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
count = (EP2BCH << 8) + EP2BCL;
// for(i=0;i<count;i++)
// SendData(*(EP2FIFOBUF+i));
//EZUSB_Delay(400);
LEDIO=!LEDIO;
EP2BCL = 0x80; // re(arm) EP2OUT
}*/
if(!in_enable) return;
if(!AD_IRQ)
{
//cmd_buffer[0]='P';
//WriteCMD_GPIF(cmd_buffer);
LEDIO=0;
EZUSB_Delay(10);
if(AD_IRQ)return;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
GPIFTCB3=0;
SYNCDELAY;
GPIFTCB2=0;
SYNCDELAY;
GPIFTCB1 = 0x4;//MSB(Tcount); // setup transaction count with Tcount value
SYNCDELAY;
GPIFTCB0 = 0x00;//LSB(Tcount);
SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6IN
SYNCDELAY;
SYNCDELAY;
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
LEDIO=1;
EZUSB_Delay(10);
cmd_buffer[0]='R';
WriteCMD_GPIF(cmd_buffer);
// cmd_buffer[0]='R';
// WriteCMD_GPIF(cmd_buffer);
}
/*
SYNCDELAY;
xFIFOBC_IN = ( ( EP6FIFOBCH << 8 ) + EP6FIFOBCL ); // get EP6FIFOBCH/L value
if( xFIFOBC_IN < 0x0200 ) // if pkt is short,
{
INPKTEND = 0x06; // force a commit to the host
}
*/
/*
if(in_enable) // if IN transfers are enabled,
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
SYNCDELAY;
GPIFTCB1 = 0x10;//MSB(Tcount); // setup transaction count with Tcount value
SYNCDELAY;
GPIFTCB0 = 0x0;//LSB(Tcount);
SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6IN
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
SYNCDELAY;
xFIFOBC_IN = ( ( EP6FIFOBCH << 8 ) + EP6FIFOBCL ); // get EP6FIFOBCH/L value
if( xFIFOBC_IN < 0x0200 ) // if pkt is short,
{
INPKTEND = 0x06; // force a commit to the host
}
LEDIO=0;
EZUSB_Delay(30);
LEDIO=1;
EZUSB_Delay(30);
cmd_buffer[0]='R';
WriteCMD_GPIF(cmd_buffer);
in_enable=0;
EX0 = 1;
}
*/
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
if( EZUSB_HIGHSPEED( ) )
{ // FX2 enumerated at high speed
SYNCDELAY; //
EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
SYNCDELAY; //
EP6AUTOINLENL = 0x00;
SYNCDELAY;
enum_high_speed = TRUE;
}
else
{ // FX2 enumerated at full speed
SYNCDELAY;
EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
enum_high_speed = FALSE;
}
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
AlternateSetting = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
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