📄 laguna.c
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else l->bclk=laguna_readb(0x8c); l->tile=laguna_readb(0x407) & 0x3f; /* no interleave */ offset = modeinfo->lineWidth >> 3; moderegs[0x13]=offset&0xff; hd = (modetiming->CrtcHDisplay >> 3) - 1; htot = (modetiming->CrtcHTotal >> 3) - 5; hss = (modetiming->CrtcHSyncStart >> 3); hse = (modetiming->CrtcHSyncEnd >> 3); hbs = (modetiming->CrtcHSyncStart >> 3) - 1; hbe = (modetiming->CrtcHSyncEnd >> 3); vd = modetiming->CrtcVDisplay - 1; vtot = modetiming->CrtcVTotal - 2; vss = modetiming->CrtcVSyncStart; vse = modetiming->CrtcVSyncEnd; vbs = modetiming->CrtcVSyncStart - 1; vbe = modetiming->CrtcVSyncEnd; l->crt[0] = htot>>1; l->crt[1] = ((vbe>>2)&0xf0) | /* vertical blank end overflow */ 2; /* double buffered display start */ if (modetiming->flags & INTERLACED) l->crt[1] |= 0x1; l->crt[2] = 0x22 | /* extended address and no border*/ ((offset&0x100)>>4); l->crt[3]=(offset&0x200)>>9; l->crt[4] = ((htot&0x100)>>1) | ((hd&0x100)>>2) | ((hbs&0x100)>>3) | ((hss&0x100)>>4) | ((vtot&0x400)>>7) | ((vd&0x400)>>8) | ((vbs&0x400)>>9) | ((vss&0x400)>>10); l->gra[0]=0; l->gra[2]=32; /* use 16KB granularity, only one bank */ if(laguna_findclock(modetiming->pixelClock,&n,&m,&p,&pp)) { /* should not happen */ exit(4); } l->seq[0]=(m<<1)|p; l->seq[1]=n; l->seq[2]=1; l->pal_state=0; l->format=pp>>14; switch(modeinfo->bitsPerPixel) { case 8: l->format|=0; l->control |= 0; break; case 15: case 16: if(modeinfo->greenWeight==5) l->format|=0x1600; else l->format|=0x1400; l->control |= 0x2000; break; case 24: l->format|=0x2400; l->control |= 0x4000; break; case 32: l->format|=0x3400; l->control |= 0x6000; break; } l->cur_misc=0; /* disable cursor */ l->cur_preset=0; moderegs[59] |= 0x0c; return;}static int laguna_setmode(int mode, int prv_mode){ unsigned char *moderegs; ModeTiming *modetiming; ModeInfo *modeinfo; if ((mode < G640x480x256)||(mode==G720x348x2)) { laguna_writeb(0xe6,0); __svgalib_outseq(0x07,0); return __svgalib_vga_driverspecs.setmode(mode, prv_mode); } if (!laguna_modeavailable(mode)) return 1; modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode); modetiming = malloc(sizeof(ModeTiming)); if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) { free(modetiming); free(modeinfo); return 1; } moderegs = malloc(LAGUNA_TOTAL_REGS); laguna_initializemode(moderegs, modetiming, modeinfo, mode); free(modetiming); __svgalib_setregs(moderegs); /* Set standard regs. */ laguna_setregs(moderegs, mode); /* Set extended regs. */ free(moderegs); __svgalib_InitializeAcceleratorInterface(modeinfo); free(modeinfo); return 0;}/* Unlock chipset-specific registers */static void laguna_unlock(void){ __svgalib_outcrtc(0x11,__svgalib_incrtc(0x11)&0x7f);}static void laguna_lock(void){}#define VENDOR_ID 0x1013/* Indentify chipset, initialize and return non-zero if detected */static int laguna_test(void){ int found; unsigned long buf[64]; found=__svgalib_pci_find_vendor_vga(VENDOR_ID,buf,0); if(!found&& ((((buf[0]>>16)&0xffff)==0x00d0)|| (((buf[0]>>16)&0xffff)==0x00d4)|| (((buf[0]>>16)&0xffff)==0x00d6))){ laguna_init(0,0,0); return 1; }; return 0;}/* Set display start address (not for 16 color modes) *//* Cirrus supports any address in video memory (up to 2Mb) */static void laguna_setdisplaystart(int address){ address=address >> 2; __svgalib_outcrtc(0x0c,(address & 0xFF00)>>8); __svgalib_outcrtc(0x0d, address & 0xFF); __svgalib_outcrtc(0x1b, (__svgalib_incrtc(0x1b)&0xf2) | ((address&0x100)>>8) | ((address&0x600)>>7)); __svgalib_outcrtc(0x1d, (__svgalib_incrtc(0x1b)&0xe7) | ((address&0x1800)>>8) ); }/* Set logical scanline length (usually multiple of 8) *//* Cirrus supports multiples of 8, up to 4088 */static void laguna_setlogicalwidth(int width){ int offset = width >> 3; __svgalib_outcrtc(0x13,offset&0xff); __svgalib_outcrtc(0x1b, (__svgalib_incrtc(0x1b)&0xef)| ((offset&0x100)>>4)); __svgalib_outcrtc(0x1d, (__svgalib_incrtc(0x1b)&0xfe)| ((offset&0x200)>>9));}static int laguna_linear(int op, int param){ if (op==LINEAR_ENABLE){laguna_is_linear=1; return 0;}; if (op==LINEAR_DISABLE){laguna_is_linear=0; return 0;}; if (op==LINEAR_QUERY_BASE) return laguna_linear_base; if (op == LINEAR_QUERY_RANGE || op == LINEAR_QUERY_GRANULARITY) return 0; /* No granularity or range. */ else return -1; /* Unknown function. */}static int laguna_match_programmable_clock(int clock){return clock ;}static int laguna_map_clock(int bpp, int clock){return clock ;}static int laguna_map_horizontal_crtc(int bpp, int pixelclock, int htiming){return htiming;}/* Function table (exported) */DriverSpecs __svgalib_laguna_driverspecs ={ laguna_saveregs, laguna_setregs, laguna_unlock, laguna_lock, laguna_test, laguna_init, laguna_setpage, NULL, NULL, laguna_setmode, laguna_modeavailable, laguna_setdisplaystart, laguna_setlogicalwidth, laguna_getmodeinfo, 0, /* old blit funcs */ 0, 0, 0, 0, 0, /* ext_set */ 0, /* accel */ laguna_linear, 0, /* accelspecs, filled in during init. */ NULL, /* Emulation */};/* Initialize chipset (called after detection) */static int laguna_init(int force, int par1, int par2){ unsigned long buf[64]; int found=0; char *chipnames[]={"5462", "5464", "5465"}; laguna_unlock(); if (force) { laguna_memory = par1; laguna_chiptype = par2; } else { }; found=__svgalib_pci_find_vendor_vga(VENDOR_ID,buf,0); laguna_linear_base=0; if (!found){ laguna_mmio_base=buf[4]&0xffffff00; laguna_linear_base=buf[5]&0xffffff00; switch(buf[0]>>16) { case 0xd0: laguna_chiptype=L5462; break; case 0xd4: laguna_chiptype=L5464; break; case 0xd6: laguna_chiptype=L5465; break; } laguna_memory=((__svgalib_inseq(0x14)&0x07)+1)*1024; } else return -1; if (__svgalib_driver_report) { printf("Using LAGUNA driver, %s with %iKB video ram found.\n", chipnames[laguna_chiptype],laguna_memory); }; cardspecs = malloc(sizeof(CardSpecs)); cardspecs->videoMemory = laguna_memory; cardspecs->maxPixelClock4bpp = 170000; switch(laguna_chiptype) { case L5462: cardspecs->maxPixelClock8bpp = 170000; cardspecs->maxPixelClock16bpp = 135100; cardspecs->maxPixelClock24bpp = 135100; cardspecs->maxPixelClock32bpp = 85500; case L5464: cardspecs->maxPixelClock8bpp = 230000; cardspecs->maxPixelClock16bpp = 170000; cardspecs->maxPixelClock24bpp = 170000; cardspecs->maxPixelClock32bpp = 135100; case L5465: cardspecs->maxPixelClock8bpp = 250000; cardspecs->maxPixelClock16bpp = 170000; cardspecs->maxPixelClock24bpp = 170000; cardspecs->maxPixelClock32bpp = 135100; } cardspecs->flags = INTERLACE_DIVIDE_VERT | CLOCK_PROGRAMMABLE; cardspecs->maxHorizontalCrtc = 4088; cardspecs->nClocks =0; cardspecs->mapClock = laguna_map_clock; cardspecs->mapHorizontalCrtc = laguna_map_horizontal_crtc; cardspecs->matchProgrammableClock=laguna_match_programmable_clock; __svgalib_driverspecs = &__svgalib_laguna_driverspecs; __svgalib_banked_mem_base=0xa0000; __svgalib_banked_mem_size=0x10000; __svgalib_linear_mem_base=laguna_linear_base; __svgalib_linear_mem_size=laguna_memory*0x400; __svgalib_mmio_base=laguna_mmio_base; __svgalib_mmio_size=4096; return 0;}
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