📄 r128_reg.h
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#define R128_OV0_P1_V_ACCUM_INIT 0x0428# define R128_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L# define R128_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L#define R128_OV0_P23_V_ACCUM_INIT 0x042C#define R128_OV0_P1_BLANK_LINES_AT_TOP 0x0430# define R128_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL# define R128_P1_ACTIVE_LINES_M1 0x0fff0000L#define R128_OV0_P23_BLANK_LINES_AT_TOP 0x0434# define R128_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL# define R128_P23_ACTIVE_LINES_M1 0x07ff0000L#define R128_OV0_VID_BUF0_BASE_ADRS 0x0440# define R128_VIF_BUF0_PITCH_SEL 0x00000001L# define R128_VIF_BUF0_TILE_ADRS 0x00000002L# define R128_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L# define R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L#define R128_OV0_VID_BUF1_BASE_ADRS 0x0444# define R128_VIF_BUF1_PITCH_SEL 0x00000001L# define R128_VIF_BUF1_TILE_ADRS 0x00000002L# define R128_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L# define R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L#define R128_OV0_VID_BUF2_BASE_ADRS 0x0448# define R128_VIF_BUF2_PITCH_SEL 0x00000001L# define R128_VIF_BUF2_TILE_ADRS 0x00000002L# define R128_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L# define R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L#define R128_OV0_VID_BUF3_BASE_ADRS 0x044C#define R128_OV0_VID_BUF4_BASE_ADRS 0x0450#define R128_OV0_VID_BUF5_BASE_ADRS 0x0454#define R128_OV0_VID_BUF_PITCH0_VALUE 0x0460#define R128_OV0_VID_BUF_PITCH1_VALUE 0x0464#define R128_OV0_AUTO_FLIP_CNTL 0x0470#define R128_OV0_DEINTERLACE_PATTERN 0x0474#define R128_OV0_H_INC 0x0480#define R128_OV0_STEP_BY 0x0484#define R128_OV0_P1_H_ACCUM_INIT 0x0488#define R128_OV0_P23_H_ACCUM_INIT 0x048C#define R128_OV0_P1_X_START_END 0x0494#define R128_OV0_P2_X_START_END 0x0498#define R128_OV0_P3_X_START_END 0x049C#define R128_OV0_FILTER_CNTL 0x04A0#define R128_OV0_FOUR_TAP_COEF_0 0x04B0#define R128_OV0_FOUR_TAP_COEF_1 0x04B4#define R128_OV0_FOUR_TAP_COEF_2 0x04B8#define R128_OV0_FOUR_TAP_COEF_3 0x04BC#define R128_OV0_FOUR_TAP_COEF_4 0x04C0#define R128_OV0_COLOUR_CNTL 0x04E0#define R128_OV0_VIDEO_KEY_CLR 0x04E4#define R128_OV0_VIDEO_KEY_MSK 0x04E8#define R128_OV0_GRAPHICS_KEY_CLR 0x04EC#define R128_OV0_GRAPHICS_KEY_MSK 0x04F0#define R128_OV0_KEY_CNTL 0x04F4# define R128_VIDEO_KEY_FN_MASK 0x00000007L# define R128_VIDEO_KEY_FN_FALSE 0x00000000L# define R128_VIDEO_KEY_FN_TRUE 0x00000001L# define R128_VIDEO_KEY_FN_EQ 0x00000004L# define R128_VIDEO_KEY_FN_NE 0x00000005L# define R128_GRAPHIC_KEY_FN_MASK 0x00000070L# define R128_GRAPHIC_KEY_FN_FALSE 0x00000000L# define R128_GRAPHIC_KEY_FN_TRUE 0x00000010L# define R128_GRAPHIC_KEY_FN_EQ 0x00000040L# define R128_GRAPHIC_KEY_FN_NE 0x00000050L# define R128_CMP_MIX_MASK 0x00000100L# define R128_CMP_MIX_OR 0x00000000L# define R128_CMP_MIX_AND 0x00000100L#define R128_OV0_TEST 0x04F8#define R128_PALETTE_DATA 0x00b4#define R128_PALETTE_INDEX 0x00b0#define R128_PC_DEBUG_MODE 0x1760#define R128_PC_GUI_CTLSTAT 0x1748#define R128_PC_GUI_MODE 0x1744# define R128_PC_IGNORE_UNIFY (1 << 5)#define R128_PC_MISC_CNTL 0x0188#define R128_PC_NGUI_CTLSTAT 0x0184# define R128_PC_FLUSH_GUI (3 << 0)# define R128_PC_RI_GUI (1 << 2)# define R128_PC_FLUSH_ALL 0x00ff# define R128_PC_BUSY (1 << 31)#define R128_PC_NGUI_MODE 0x0180#define R128_PCI_GART_PAGE 0x017c#define R128_PLANE_3D_MASK_C 0x1d44#define R128_PLL_TEST_CNTL 0x0013 /* PLL */#define R128_PMI_CAP_ID 0x0f5c /* PCI */#define R128_PMI_DATA 0x0f63 /* PCI */#define R128_PMI_NXT_CAP_PTR 0x0f5d /* PCI */#define R128_PMI_PMC_REG 0x0f5e /* PCI */#define R128_PMI_PMCSR_REG 0x0f60 /* PCI */#define R128_PMI_REGISTER 0x0f5c /* PCI */#define R128_PPLL_CNTL 0x0002 /* PLL */# define R128_PPLL_RESET (1 << 0)# define R128_PPLL_SLEEP (1 << 1)# define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16)# define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)#define R128_PPLL_DIV_0 0x0004 /* PLL */#define R128_PPLL_DIV_1 0x0005 /* PLL */#define R128_PPLL_DIV_2 0x0006 /* PLL */#define R128_PPLL_DIV_3 0x0007 /* PLL */# define R128_PPLL_FB3_DIV_MASK 0x07ff# define R128_PPLL_POST3_DIV_MASK 0x00070000#define R128_PPLL_REF_DIV 0x0003 /* PLL */# define R128_PPLL_REF_DIV_MASK 0x03ff# define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */# define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */#define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */#define R128_REG_BASE 0x0f18 /* PCI */#define R128_REGPROG_INF 0x0f09 /* PCI */#define R128_REVISION_ID 0x0f08 /* PCI */#define R128_SC_BOTTOM 0x164c#define R128_SC_BOTTOM_RIGHT 0x16f0#define R128_SC_BOTTOM_RIGHT_C 0x1c8c#define R128_SC_LEFT 0x1640#define R128_SC_RIGHT 0x1644#define R128_SC_TOP 0x1648#define R128_SC_TOP_LEFT 0x16ec#define R128_SC_TOP_LEFT_C 0x1c88#define R128_SEQ8_DATA 0x03c5 /* VGA */#define R128_SEQ8_IDX 0x03c4 /* VGA */#define R128_SNAPSHOT_F_COUNT 0x0244#define R128_SNAPSHOT_VH_COUNTS 0x0240#define R128_SNAPSHOT_VIF_COUNT 0x024c#define R128_SRC_OFFSET 0x15ac#define R128_SRC_PITCH 0x15b0#define R128_SRC_PITCH_OFFSET 0x1428#define R128_SRC_SC_BOTTOM 0x165c#define R128_SRC_SC_BOTTOM_RIGHT 0x16f4#define R128_SRC_SC_RIGHT 0x1654#define R128_SRC_X 0x1414#define R128_SRC_X_Y 0x1590#define R128_SRC_Y 0x1418#define R128_SRC_Y_X 0x1434#define R128_STATUS 0x0f06 /* PCI */#define R128_SUBPIC_CNTL 0x0540 /* ? */#define R128_SUB_CLASS 0x0f0a /* PCI */#define R128_SURFACE_DELAY 0x0b00#define R128_SURFACE0_INFO 0x0b0c#define R128_SURFACE0_LOWER_BOUND 0x0b04#define R128_SURFACE0_UPPER_BOUND 0x0b08#define R128_SURFACE1_INFO 0x0b1c#define R128_SURFACE1_LOWER_BOUND 0x0b14#define R128_SURFACE1_UPPER_BOUND 0x0b18#define R128_SURFACE2_INFO 0x0b2c#define R128_SURFACE2_LOWER_BOUND 0x0b24#define R128_SURFACE2_UPPER_BOUND 0x0b28#define R128_SURFACE3_INFO 0x0b3c#define R128_SURFACE3_LOWER_BOUND 0x0b34#define R128_SURFACE3_UPPER_BOUND 0x0b38#define R128_SW_SEMAPHORE 0x013c#define R128_TEST_DEBUG_CNTL 0x0120#define R128_TEST_DEBUG_MUX 0x0124#define R128_TEST_DEBUG_OUT 0x012c#define R128_TMDS_CRC 0x02a0#define R128_TRAIL_BRES_DEC 0x1614#define R128_TRAIL_BRES_ERR 0x160c#define R128_TRAIL_BRES_INC 0x1610#define R128_TRAIL_X 0x1618#define R128_TRAIL_X_SUB 0x1620#define R128_VCLK_ECP_CNTL 0x0008 /* PLL */#define R128_VENDOR_ID 0x0f00 /* PCI */#define R128_VGA_DDA_CONFIG 0x02e8#define R128_VGA_DDA_ON_OFF 0x02ec#define R128_VID_BUFFER_CONTROL 0x0900#define R128_VIDEOMUX_CNTL 0x0190#define R128_VIPH_CONTROL 0x01D0 /* ? */#define R128_WAIT_UNTIL 0x1720#define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */#define R128_XCLK_CNTL 0x000d /* PLL */#define R128_XDLL_CNTL 0x000c /* PLL */#define R128_XPLL_CNTL 0x000b /* PLL */ /* Registers for CCE and Microcode Engine */#define R128_PM4_MICROCODE_ADDR 0x07d4#define R128_PM4_MICROCODE_RADDR 0x07d8#define R128_PM4_MICROCODE_DATAH 0x07dc#define R128_PM4_MICROCODE_DATAL 0x07e0#define R128_PM4_BUFFER_OFFSET 0x0700#define R128_PM4_BUFFER_CNTL 0x0704# define R128_PM4_NONPM4 (0 << 28)# define R128_PM4_192PIO (1 << 28)# define R128_PM4_192BM (2 << 28)# define R128_PM4_128PIO_64INDBM (3 << 28)# define R128_PM4_128BM_64INDBM (4 << 28)# define R128_PM4_64PIO_128INDBM (5 << 28)# define R128_PM4_64BM_128INDBM (6 << 28)# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)#define R128_PM4_BUFFER_WM_CNTL 0x0708# define R128_WMA_SHIFT 0# define R128_WMB_SHIFT 8# define R128_WMC_SHIFT 16# define R128_WB_WM_SHIFT 24#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c#define R128_PM4_BUFFER_DL_RPTR 0x0710#define R128_PM4_BUFFER_DL_WPTR 0x0714# define R128_PM4_BUFFER_DL_DONE (1 << 31)#define R128_PM4_BUFFER_DL_WPTR_DELAY 0x0718# define R128_PRE_WRITE_TIMER_SHIFT 0# define R128_PRE_WRITE_LIMIT_SHIFT 23#define R128_PM4_VC_FPU_SETUP 0x071c# define R128_FRONT_DIR_CW (0 << 0)# define R128_FRONT_DIR_CCW (1 << 0)# define R128_FRONT_DIR_MASK (1 << 0)# define R128_BACKFACE_CULL (0 << 1)# define R128_BACKFACE_POINTS (1 << 1)# define R128_BACKFACE_LINES (2 << 1)# define R128_BACKFACE_SOLID (3 << 1)# define R128_BACKFACE_MASK (3 << 1)# define R128_FRONTFACE_CULL (0 << 3)# define R128_FRONTFACE_POINTS (1 << 3)# define R128_FRONTFACE_LINES (2 << 3)# define R128_FRONTFACE_SOLID (3 << 3)# define R128_FRONTFACE_MASK (3 << 3)# define R128_FPU_COLOR_SOLID (0 << 5)# define R128_FPU_COLOR_FLAT (1 << 5)# define R128_FPU_COLOR_GOURAUD (2 << 5)# define R128_FPU_COLOR_GOURAUD2 (3 << 5)# define R128_FPU_COLOR_MASK (3 << 5)# define R128_FPU_SUB_PIX_2BITS (0 << 7)# define R128_FPU_SUB_PIX_4BITS (1 << 7)# define R128_FPU_MODE_2D (0 << 8)# define R128_FPU_MODE_3D (1 << 8)# define R128_TRAP_BITS_DISABLE (1 << 9)# define R128_EDGE_ANTIALIAS (1 << 10)# define R128_SUPERSAMPLE (1 << 11)# define R128_XFACTOR_2 (0 << 12)# define R128_XFACTOR_4 (1 << 12)# define R128_YFACTOR_2 (0 << 13)# define R128_YFACTOR_4 (1 << 13)# define R128_FLAT_SHADE_VERTEX_D3D (0 << 14)# define R128_FLAT_SHADE_VERTEX_OGL (1 << 14)# define R128_FPU_ROUND_TRUNCATE (0 << 15)# define R128_FPU_ROUND_NEAREST (1 << 15)# define R128_WM_SEL_8DW (0 << 16)# define R128_WM_SEL_16DW (1 << 16)# define R128_WM_SEL_32DW (2 << 16)#define R128_PM4_VC_DEBUG_CONFIG 0x07a4#define R128_PM4_VC_STAT 0x07a8#define R128_PM4_VC_TIMESTAMP0 0x07b0#define R128_PM4_VC_TIMESTAMP1 0x07b4#define R128_PM4_STAT 0x07b8# define R128_PM4_FIFOCNT_MASK 0x0fff# define R128_PM4_BUSY (1 << 16)# define R128_PM4_GUI_ACTIVE (1 << 31)#define R128_PM4_BUFFER_ADDR 0x07f0#define R128_PM4_MICRO_CNTL 0x07fc# define R128_PM4_MICRO_FREERUN (1 << 30)#define R128_PM4_FIFO_DATA_EVEN 0x1000#define R128_PM4_FIFO_DATA_ODD 0x1004⌨️ 快捷键说明
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