rage.c

linux 下svgalib编的一个界面程序示例

static int rage_memory,rage_chiptyperev;
static int rage_is_linear=0 , rage_linear_base;
static int ATIIODecoding;
static int ATIIOBase;
static int postdiv[8]={1,2,4,8,3,0,6,12};
static int rage_bpp;
static int M, minN, maxN, Nadj;
static double fref;
static int ATIClockToProgram;
static int ATIChip, ATIMemoryType;
static int rage_dac=0, rage_clock=0;

static CardSpecs *cardspecs;

static void rage_ChipID(void)
{
   int ATIChipType, ATIChipClass, ATIChipRevision, ATIChipVersion,
       ATIChipFoundry;
    unsigned int IO_Value = inl(ATIIOPort(CONFIG_CHIP_ID));
    ATIChipType     = GetBits(IO_Value, 0xFFFFU);
    ATIChipClass    = GetBits(IO_Value, CFG_CHIP_CLASS);
    ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REV);
    ATIChipVersion  = GetBits(IO_Value, CFG_CHIP_VERSION);
    ATIChipFoundry  = GetBits(IO_Value, CFG_CHIP_FOUNDRY);
    switch (ATIChipType)
    {
        case 0x00D7U:
            ATIChipType = 0x4758U;
        case 0x4758U:
            switch (ATIChipRevision)
            {
                case 0x00U:
                    ATIChip = ATI_CHIP_88800GXC;
                    break;

                case 0x01U:
                    ATIChip = ATI_CHIP_88800GXD;
                    break;

                case 0x02U:
                    ATIChip = ATI_CHIP_88800GXE;
                    break;

                case 0x03U:
                    ATIChip = ATI_CHIP_88800GXF;
                    break;

                default:
                    ATIChip = ATI_CHIP_88800GX;
                    break;
            }
            break;

        case 0x0057U:
            ATIChipType = 0x4358U;
        case 0x4358U:
            ATIChip = ATI_CHIP_88800CX;
            break;

        case 0x0053U:
            ATIChipType = 0x4354U;
        case 0x4354U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264CT;
            break;

        case 0x0093U:
            ATIChipType = 0x4554U;
        case 0x4554U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264ET;
            break;

        case 0x02B3U:
            ATIChipType = 0x5654U;
        case 0x5654U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264VT;
            /* Some early GT's are detected as VT's */
/*            if (ExpectedChipType && (ATIChipType != ExpectedChipType))
            {
                if (ExpectedChipType == 0x4754U)
                    ATIChip = ATI_CHIP_264GT;
                else 
                    ErrorF("Mach64 chip type probe discrepancy detected:\n"
                           " PCI=0x%04X;  CHIP_ID=0x%04X.\n",
                           ExpectedChipType, ATIChipType);
            }
            else */if (ATIChipVersion)
                ATIChip = ATI_CHIP_264VTB;
            break;

        case 0x00D3U:
            ATIChipType = 0x4754U;
        case 0x4754U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            if (!ATIChipVersion)
                ATIChip = ATI_CHIP_264GT;
            else
                ATIChip = ATI_CHIP_264GTB;
            break;

        case 0x02B4U:
            ATIChipType = 0x5655U;
        case 0x5655U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264VT3;
            break;

        case 0x00D4U:
            ATIChipType = 0x4755U;
        case 0x4755U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264GTDVD;
            break;

        case 0x0166U:
            ATIChipType = 0x4C47U;
        case 0x4C47U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264LT;
            break;

        case 0x0315U:
            ATIChipType = 0x5656U;
        case 0x5656U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264VT4;
            break;

        case 0x00D5U:
            ATIChipType = 0x4756U;
        case 0x4756U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264GT2C;
            break;

        case 0x00D6U:
        case 0x00D9U:
            ATIChipType = 0x4757U;
        case 0x4757U:
        case 0x475AU:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264GT2C;
            break;

        case 0x00CEU:
        case 0x00CFU:
        case 0x00D0U:
            ATIChipType = 0x4750U;
        case 0x4749U:
        case 0x4750U:
        case 0x4751U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264GTPRO;
            break;

        case 0x00C7U:
        case 0x00C9U:
            ATIChipType = 0x4742U;
        case 0x4742U:
        case 0x4744U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264GTPRO;
            break;

        case 0x0168U:
        case 0x016FU:
            ATIChipType = 0x4C50U;
        case 0x4C49U:
        case 0x4C50U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264LTPRO;
            break;

        case 0x0161U:
        case 0x0163U:
            ATIChipType = 0x4C42U;
        case 0x4C42U:
        case 0x4C44U:
            ATIChipRevision = GetBits(IO_Value, CFG_CHIP_REVISION);
            ATIChip = ATI_CHIP_264LTPRO;
            break;

        default:
            ATIChip = ATI_CHIP_Mach64;
            break;
    }
};

static int rage_probe(void)
{
    unsigned int i=inl(ATIIOPort(SCRATCH_REG0));
    outl(ATIIOPort(SCRATCH_REG0),0x55555555);
    if(inl(ATIIOPort(SCRATCH_REG0))!=0x55555555) {
       outl(ATIIOPort(SCRATCH_REG0),i);
       return 0;
    };
    outl(ATIIOPort(SCRATCH_REG0),0xaaaaaaaa);
    if(inl(ATIIOPort(SCRATCH_REG0))!=0xaaaaaaaa) {
       outl(ATIIOPort(SCRATCH_REG0),i);
       return 0;
    };
    outl(ATIIOPort(SCRATCH_REG0),i);

    return 1;
};

static int
ATIDivide(int Numerator, int Denominator, int Shift, const int RoundingKind)
{
    int Multiplier, Divider;
    int Rounding = 0;                           /* Default to floor */

    /* Deal with right shifts */
    if (Shift < 0)
    {
        Divider = (Numerator - 1) ^ Numerator;
        Multiplier = 1 << (-Shift);
        if (Divider > Multiplier)
            Divider = Multiplier;
        Numerator /= Divider;
        Denominator *= Multiplier / Divider;
        Shift = 0;
    }

    if (!RoundingKind)                          /* Nearest */
        Rounding = Denominator >> 1;
    else if (RoundingKind > 0)                  /* Ceiling */
        Rounding = Denominator - 1;

    return ((Numerator / Denominator) << Shift) +
            ((((Numerator % Denominator) << Shift) + Rounding) / Denominator);
}

static void rage_setpage(int page)
{
    page*=2;
    outl(ATIIOPortMEM_VGA_WP_SEL, page | ((page+1)<<16));
    outl(ATIIOPortMEM_VGA_RP_SEL, page | ((page+1)<<16));
}

static void rage_setrdpage(int page)
{
    page*=2;
    outl(ATIIOPortMEM_VGA_RP_SEL, page | ((page+1)<<16));
}

static void rage_setwrpage(int page)
{
    page*=2;
    outl(ATIIOPortMEM_VGA_WP_SEL, page | ((page+1)<<16));
}

static int __svgalib_rage_inlinearmode(void)
{
return rage_is_linear;
}

/* Fill in chipset specific mode information */

static void rage_getmodeinfo(int mode, vga_modeinfo *modeinfo)
{

    if(modeinfo->colors==16)return;

    modeinfo->maxpixels = rage_memory*1024/modeinfo->bytesperpixel;
    modeinfo->maxlogicalwidth = 4088;
    modeinfo->startaddressrange = rage_memory * 1024 - 1;
    modeinfo->haveblit = 0;
    modeinfo->flags &= ~HAVE_RWPAGE;
    modeinfo->flags |= HAVE_RWPAGE;

    if (modeinfo->bytesperpixel >= 1) {
	if(rage_linear_base)modeinfo->flags |= CAPABLE_LINEAR;
        if (__svgalib_rage_inlinearmode())
	    modeinfo->flags |= IS_LINEAR;
    }
}

/* Read and save chipset-specific registers */

int rage_saveregs(unsigned char regs[])
{ 
  ATIHWPtr save;
  int i;

  save=(ATIHWPtr)(regs+VGA_TOTAL_REGS);

/* This are needed for calling this function, without vga_init first */
/*    
    ATIIODecoding=1;
    ATIIOBase=0xd000;
    ATIIOPortCRTC_H_TOTAL_DISP=ATIIOPort(CRTC_H_TOTAL_DISP);
    ATIIOPortCRTC_H_SYNC_STRT_WID=ATIIOPort(CRTC_H_SYNC_STRT_WID);
    ATIIOPortCRTC_V_TOTAL_DISP=ATIIOPort(CRTC_V_TOTAL_DISP);
    ATIIOPortCRTC_V_SYNC_STRT_WID=ATIIOPort(CRTC_V_SYNC_STRT_WID);
    ATIIOPortCRTC_OFF_PITCH=ATIIOPort(CRTC_OFF_PITCH);
    ATIIOPortCRTC_INT_CNTL=ATIIOPort(CRTC_INT_CNTL);
    ATIIOPortCRTC_GEN_CNTL=ATIIOPort(CRTC_GEN_CNTL);
    ATIIOPortDSP_CONFIG=ATIIOPort(DSP_CONFIG);
    ATIIOPortDSP_ON_OFF=ATIIOPort(DSP_ON_OFF);
    ATIIOPortOVR_CLR=ATIIOPort(OVR_CLR);
    ATIIOPortOVR_WID_LEFT_RIGHT=ATIIOPort(OVR_WID_LEFT_RIGHT);
    ATIIOPortOVR_WID_TOP_BOTTOM=ATIIOPort(OVR_WID_TOP_BOTTOM);
    ATIIOPortCLOCK_CNTL=ATIIOPort(CLOCK_CNTL);
    ATIIOPortBUS_CNTL=ATIIOPort(BUS_CNTL);
    ATIIOPortMEM_INFO=ATIIOPort(MEM_INFO);
    ATIIOPortMEM_VGA_WP_SEL=ATIIOPort(MEM_VGA_WP_SEL);
    ATIIOPortMEM_VGA_RP_SEL=ATIIOPort(MEM_VGA_RP_SEL);
    ATIIOPortDAC_REGS=ATIIOPort(DAC_REGS);
    ATIIOPortDAC_CNTL=ATIIOPort(DAC_CNTL);
    ATIIOPortGEN_TEST_CNTL=ATIIOPort(GEN_TEST_CNTL);
    ATIIOPortCONFIG_CNTL=ATIIOPort(CONFIG_CNTL);
*/
  save->crtc_gen_cntl = inl(ATIIOPortCRTC_GEN_CNTL);

  save->crtc_h_total_disp = inl(ATIIOPortCRTC_H_TOTAL_DISP);
  save->crtc_h_sync_strt_wid = inl(ATIIOPortCRTC_H_SYNC_STRT_WID);
  save->crtc_v_total_disp = inl(ATIIOPortCRTC_V_TOTAL_DISP);
  save->crtc_v_sync_strt_wid = inl(ATIIOPortCRTC_V_SYNC_STRT_WID);
  save->crtc_off_pitch = inl(ATIIOPortCRTC_OFF_PITCH);

  save->ovr_clr = inl(ATIIOPortOVR_CLR);
  save->ovr_wid_left_right = inl(ATIIOPortOVR_WID_LEFT_RIGHT);
  save->ovr_wid_top_bottom = inl(ATIIOPortOVR_WID_TOP_BOTTOM);

  save->clock_cntl = inl(ATIIOPortCLOCK_CNTL);

  save->bus_cntl = inl(ATIIOPortBUS_CNTL);

  save->mem_vga_wp_sel = inl(ATIIOPortMEM_VGA_WP_SEL);
  save->mem_vga_rp_sel = inl(ATIIOPortMEM_VGA_RP_SEL);

  save->dac_cntl = inl(ATIIOPortDAC_CNTL); /* internal DAC */

  save->config_cntl = inl(ATIIOPortCONFIG_CNTL);

  save->mem_info = inl(ATIIOPortMEM_INFO);

  save->crtc_int_cntl=inl(ATIIOPortCRTC_INT_CNTL);
  save->crtc_gen_cntl=inl(ATIIOPortCRTC_GEN_CNTL);
  save->gen_test_cntl=inl(ATIIOPortGEN_TEST_CNTL);  

  switch(rage_clock){
     case 0: /* internal clock */
        for(i=6;i<12;i++)
           save->PLL[i]=ATIGetMach64PLLReg(i); /* internal Clock */
        break;
  };

  if((ATIChip>=ATI_CHIP_264VTB)&&(ATIIODecoding==BLOCK_IO)) {
    save->dsp_on_off=inl(ATIIOPortDSP_ON_OFF);
    save->dsp_config=inl(ATIIOPortDSP_CONFIG);
  };

  ATIIOPortDAC_DATA = ATIIOPortDAC_REGS + 1;
  ATIIOPortDAC_MASK = ATIIOPortDAC_REGS + 2;
  ATIIOPortDAC_READ = ATIIOPortDAC_REGS + 3;
  ATIIOPortDAC_WRITE = ATIIOPortDAC_REGS + 0;
  save->dac_read = inb(ATIIOPortDAC_READ);
  save->dac_write = inb(ATIIOPortDAC_WRITE);
  save->dac_mask = inb(ATIIOPortDAC_MASK);

  outb(ATIIOPortDAC_MASK, 0xFFU);
  outb(ATIIOPortDAC_READ, 0x00U);
  for (i = 0;  i<DAC_SIZE;  i++)
      save->DAC[i] = inb(ATIIOPortDAC_DATA);

  switch(rage_dac){
       case 5:
          i=inl(ATIIOPortDAC_CNTL);
          outl(ATIIOPortDAC_CNTL,(i&0xfffffffc)|2);
          save->extdac[8]=inb(ATIIOPortDAC_WRITE);
          save->extdac[10]=inb(ATIIOPortDAC_MASK);
          save->extdac[11]=inb(ATIIOPortDAC_READ);
          outl(ATIIOPortDAC_CNTL,(i&0xfffffffc)|3);
          save->extdac[12]=inb(ATIIOPortDAC_WRITE);
          outl(ATIIOPortDAC_CNTL,i);
       break;
  };

  return RAGE_TOTAL_REGS - VGA_TOTAL_REGS;
}

/* Set chipset-specific registers */

static void rage_setregs(const unsigned char regs[], int mode)
{  
    ATIHWPtr restore;
    int Index;    
    int i;

    restore=(ATIHWPtr)(regs+VGA_TOTAL_REGS);

    outl(ATIIOPortCRTC_GEN_CNTL, restore->crtc_gen_cntl & ~CRTC_EN );

    /* Load Mach64 CRTC registers */
    outl(ATIIOPortCRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
    outl(ATIIOPortCRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
    outl(ATIIOPortCRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
    outl(ATIIOPortCRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
    outl(ATIIOPortCRTC_OFF_PITCH, restore->crtc_off_pitch);
    /* Set pixel clock */
    outl(ATIIOPortCLOCK_CNTL, restore->clock_cntl);

    /* Load overscan registers */
    outl(ATIIOPortOVR_CLR, restore->ovr_clr);
    outl(ATIIOPortOVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
    outl(ATIIOPortOVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);

    /* Finalize CRTC setup and turn on the screen */
    outl(ATIIOPortCRTC_GEN_CNTL, restore->crtc_gen_cntl);

    /* Aperture setup */
    outl(ATIIOPortBUS_CNTL, restore->bus_cntl);

    outl(ATIIOPortMEM_VGA_WP_SEL, restore->mem_vga_wp_sel);
    outl(ATIIOPortMEM_VGA_RP_SEL, restore->mem_vga_rp_sel);

    outl(ATIIOPortCONFIG_CNTL, restore->config_cntl);

    if((ATIChip>=ATI_CHIP_264VTB)&&(ATIIODecoding==BLOCK_IO)) {