chips.c

linux 下svgalib编的一个界面程序示例

/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen                    */
/*                                                                 */
/* This library is free software; you can redistribute it and/or   */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty.   */

/* Multi-chipset support Copyright (C) 1993 Harm Hanemaayer */
/* Modified by Hartmut Schirmer */

/*----------------------------------------------------------------------*/
/* most of this code is the result of hacking round with the		*/
/* XFree86 chips & technologies driver, the tvga8900 (svgalib		*/
/* driver), vgadoc4b, the output from dumpreg (run from text mode	*/
/* and also under XFree86)						*/
/* all copyrights acknowledged						*/
/* 									*/
/* HACKED 1996 by Sergio and Angelo Masci				*/
/*		  titan.demon.co.uk					*/
/* 									*/
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
/* MODIFIED 1996 by David Bateman <[e-mail]>		*/
/* 		Added Linear Addressing					*/
/* 		Added BitBLT support					*/
/* 		Added support for the HiQV chips			*/
/* 		Programmable Clocks and XFree like modelines		*/
/* 		15/16 and 24bpp support					*/
/* MODIFIED 1998:                                                       */
/*              Added support for 65555, 68554, 69000 and 64300 chips   */
/*              Some smaller fixes (65554 memory probing, max. pixel    */
/*                                 clock)                               */
/* 									*/
/* Note that although this is a fully featured driver, it is still	*/
/* considered to be experimental. It hasn't been exhaustively tested at	*/
/* all with much code written from the specification sheets for chipset	*/
/* and architectures that the author did have available. So sucess or	*/
/* failure reports are most welcome. Please e-mail to "David Bateman	*/
/* <[e-mail]>"						*/
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
/* Fixes 1998 for ct65550 by Christian Groessler <[e-mail]>	*/
/*              - modelines work now                                    */
/*              - some smaller bugs fixed                               */
/*              - set XRE2 to BIOS video mode                           */
/*              - in vga.c: no usleep(MODESWITCHDELAY) when restoring   */
/*                textmode -> textmode streching is restored correctly. */
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
/* By default the text clock frequency is assumed to be 25.175MHz.	*/
/* at the LCD and 28.322MHz at a CRT. This can be forced to be probed	*/
/* by defining CHIPS_PROBE_TEXT_CLOCK below. Note that the probing	*/
/* process can be unreliable. Alternatively the text clock can be	*/
/* overridden from the libvga.config file with the TextClockFreq	*/
/* option.								*/
/*----------------------------------------------------------------------*/
/*
#define CHIPS_PROBE_TEXT_CLOCK
*/

/*----------------------------------------------------------------------*/
/* Normaly there is a 64K page at 0xA0000 that acts as a window		*/
/* into video RAM located on the video adaptor. This window can		*/
/* be moved around to allow all the video RAM to be accessed by		*/
/* the CPU. Some chip sets allow two different windows to share		*/
/* the same 64K page. The video adaptor differentiates between		*/
/* the two windows by using the read/write signal provided by the	*/
/* CPU, so that when it is reading from any location within the		*/
/* 64K page at 0xA0000 it is reading through the read window		*/
/* (often refered to as the read bank) and when it is writing to	*/
/* any location within the 64K page at 0xA0000 it is writing		*/
/* through the write window (often refered to as the write bank).	*/
/* This allows the CPU to move data around the video RAM without	*/
/* the overhead of continually changing the address of the window	*/
/* between reads and writes. The Chips & Technologies chip set		*/
/* does thing slightly differently. It allows the 64K page at		*/
/* 0xA0000 to be split into two 32K pages, one at 0xA0000 and the	*/
/* other at 0xA8000. These two pages provide two seperate windows	*/
/* each of which can be accessed for both reading and writing data.	*/
/*----------------------------------------------------------------------*/

#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>		/* iopl() */
#include <signal.h>		/* sigprocmask */
#include <sys/mman.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"

/* New style driver interface */
#include "timing.h"
#include "vgaregs.h"
#include "interface.h"
#include "accel.h"
#include "vgapci.h"

#define FALSE 0
#define TRUE (!FALSE)

#define ENTER TRUE
#define LEAVE FALSE
typedef int Bool;

static int CHIPSchipset;
static int video_memory;	/* amount of video memory in K */
static unsigned char ctVgaIOBaseFlag;
struct {
    int HDisplay;
    int HRetraceStart;
    int HRetraceEnd;
    int HTotal;
    int VDisplay;
    int VRetraceStart;
    int VTotal;
} __svgalib_ctSize;
static Bool ctLCD=FALSE, ctCRT=TRUE;
/* Panel Types */
unsigned char __svgalib_ctPanelType = 0;
#define TFT 1
#define SS 2			       /* STN Types */
#define DS 4
#define DD 6
#define IS_STN(X) X&6

/* Masks for which option flags have been set */
static int ctFlagsSet = 0;
#define ctFlags_LCDPanelSize	0x1
#define ctFlags_UseModeline	0x2
#define ctFlags_NoBitBlt	0x4
#define ctFlags_Use18BitBus	0x8
#define ctFlags_SetLinear	0x10
#define ctFlags_StretchEnable	0x20
#define ctFlags_StretchDisable	0x40
#define ctFlags_CenterEnable	0x80
#define ctFlags_CenterDisable	0x100

/* Global variables for acceleration support */
static unsigned int ctROP = 0; /* Default to GXcopy */
static unsigned int ctFGCOLOR;
static unsigned int ctBGCOLOR;
static unsigned int ctTRANSMODE = 0; /* Default to non transparency */
static Bool ctMMIO=FALSE;	/* Is the chip using MMIO */
unsigned char *__svgalib_ctMMIOBase = NULL;	/* MMIO base address */
unsigned int __svgalib_ctMMIOPage = -1;		/* MMIO paged base address */
unsigned int __svgalib_CHIPS_LinearBase = -1; /* Linear FrameBuffer address */
unsigned char *__svgalib_ctBltDataWindow = NULL; /* Window for Monochrome src data */

static void * MMIO_mem1, * MMIO_mem2;

static int ct_video_mode(int bpp, int weight_green, int display_size);

/* Forward definitions for accelerated support */
static void CHIPS_ScreenCopy(int x1, int y1, int x2, int y2, int w, int h);
static void CHIPS_mmio_ScreenCopy(int x1, int y1, int x2, int y2, int w, 
				  int h);
static void CHIPS_hiqv_ScreenCopy(int x1, int y1, int x2, int y2, int w, 
				  int h);
void __svgalib_CHIPS_FillBox(int x, int y, int width, int height);
void __svgalib_CHIPS_mmio_FillBox(int x, int y, int width, int height);
void __svgalib_CHIPS_hiqv_FillBox(int x, int y, int width, int height);
void __svgalib_CHIPS_FillBox24(int x, int y, int width, int height);
void __svgalib_CHIPS_mmio_FillBox24(int x, int y, int width, int height);
void __svgalib_CHIPS_PutBitmap(int x, int y, int w, int h, void *bitmap);
void __svgalib_CHIPS_mmio_PutBitmap(int x, int y, int w, int h, void *bitmap);
void __svgalib_CHIPS_hiqv_PutBitmap(int x, int y, int w, int h, void *bitmap);
void __svgalib_CHIPS_SetRasterOp(int rop);
void __svgalib_CHIPS_SetBGColor(int fg);
void __svgalib_CHIPS_SetFGColor(int fg);
static void CHIPS_Sync(void);
static void CHIPS_mmio_Sync(void);
static void CHIPS_hiqv_Sync(void);
void __svgalib_CHIPS_SetTransparency(int mode, int color);

/* alu to C&T conversion for use with source data */
static unsigned int ctAluConv[] =
{
    0xCC,			/* ROP_COPY   : dest = src; GXcopy */
    0xEE,			/* ROP_OR     : dest |= src; GXor */
    0x88,			/* ROP_AND    : dest &= src; GXand */
    0x66,			/* ROP_XOR    : dest = ^src; GXxor */
    0x55,			/* ROP_INVERT : dest = ~dest; GXInvert */
};
/* alu to C&T conversion for use with pattern data */
static unsigned int ctAluConv2[] =
{
    0xF0,			/* ROP_COPY   : dest = src; GXcopy */
    0xFC,			/* ROP_OR     : dest |= src; GXor */
    0xA0,			/* ROP_AND    : dest &= src; GXand */
    0x5A,			/* ROP_XOR    : dest = ^src; GXxor */
    0x55,			/* ROP_INVERT : dest = ~dest; GXInvert */
};

/* Bitwise reversal of bytes, required for monochrome source expansion */
unsigned char __svgalib_byte_reversed[256] =
{
    0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
    0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
    0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
    0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
    0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
    0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
    0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
    0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
    0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
    0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
    0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
    0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
    0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
    0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
    0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
    0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
    0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
    0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
    0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
    0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
    0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
    0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
    0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
    0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
    0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
    0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
    0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
    0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
    0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
    0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
    0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
    0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
};

/* Registers to save */
unsigned char __svgalib_XRregs[] =
{
0x02, 0x03, 0x04, 0x06, 0x07, 0x0B, 0x0D, 0x0F, 0x17, 0x19,
0x1A, 0x1B, 0x1C, 0x1E, 0x21, 0x22, 0x23, 0x28, 0x2C, 0x2D,
0x2F, 0x33, 0x40, 0x50, 0x51, 0x52, 0x54, 0x55, 0x56, 0x57, 
0x58, 0x5A, 0x64, 0x65, 0x66, 0x67, 0x68, 0x6F,
};
unsigned char __svgalib_HiQVXRregs[] =
{
0x09, 0x0A, 0x0E, 0x20, 0x40, 0x80, 0x81, 0xE2,
};
unsigned char __svgalib_HiQVCRregs[] =
{
0x30, 0x31, 0x32, 0x33, 0x38, 0x3C, 0x41,
};
unsigned char __svgalib_HiQVFRregs[] =
{
0x03, 0x08, 0x10, 0x11, 0x12, 0x20, 0x21, 0x22, 0x23, 0x24,
0x25, 0x26, 0x27, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
0x37, 0x40, 0x48, 0x73,
};

static int NUM_XRregs = (sizeof(__svgalib_XRregs) / sizeof(__svgalib_XRregs[0]));
static int NUM_HiQVXRregs = (sizeof(__svgalib_HiQVXRregs) / sizeof(__svgalib_HiQVXRregs[0]));
static int NUM_HiQVFRregs = (sizeof(__svgalib_HiQVFRregs) / sizeof(__svgalib_HiQVFRregs[0]));
static int NUM_HiQVCRregs = (sizeof(__svgalib_HiQVCRregs) / sizeof(__svgalib_HiQVCRregs[0]));
static int NUM_Clock = 5;
#define CHIPSREG_XR(i) (VGA_TOTAL_REGS + i)
#define CHIPSREG_HiQVXR(i) (VGA_TOTAL_REGS + NUM_XRregs + i)
#define CHIPSREG_HiQVFR(i) (VGA_TOTAL_REGS + NUM_XRregs + NUM_HiQVXRregs + i)
#define CHIPSREG_HiQVCR(i) (VGA_TOTAL_REGS + NUM_XRregs + NUM_HiQVXRregs + \
			    NUM_HiQVFRregs + i)
#define CHIPS_CLOCK(i) (VGA_TOTAL_REGS + NUM_XRregs + NUM_HiQVXRregs + \
			    NUM_HiQVFRregs + NUM_HiQVCRregs + i)
#define CHIPS_TOTAL_REGS (VGA_TOTAL_REGS + NUM_XRregs + NUM_HiQVXRregs + \
			  NUM_HiQVFRregs + NUM_HiQVCRregs + NUM_Clock)
#define MSR CHIPS_CLOCK(0)
#define VCLK(i) CHIPS_CLOCK(1 + i)
#define XR02 CHIPSREG_XR(0)
#define XR03 CHIPSREG_XR(1)
#define XR04 CHIPSREG_XR(2)
#define XR06 CHIPSREG_XR(3)
#define XR07 CHIPSREG_XR(4)
#define XR0B CHIPSREG_XR(5)
#define XR0D CHIPSREG_XR(6)
#define XR0F CHIPSREG_XR(7)
#define XR17 CHIPSREG_XR(8)
#define XR19 CHIPSREG_XR(9)
#define XR1A CHIPSREG_XR(10)
#define XR1B CHIPSREG_XR(11)
#define XR1C CHIPSREG_XR(12)
#define XR1E CHIPSREG_XR(13)
#define XR21 CHIPSREG_XR(14)
#define XR22 CHIPSREG_XR(15)
#define XR23 CHIPSREG_XR(16)
#define XR28 CHIPSREG_XR(17)
#define XR2C CHIPSREG_XR(18)
#define XR2D CHIPSREG_XR(19)
#define XR2F CHIPSREG_XR(20)
#define XR33 CHIPSREG_XR(21)
#define XR40 CHIPSREG_XR(22)
#define XR50 CHIPSREG_XR(23)
#define XR51 CHIPSREG_XR(24)
#define XR52 CHIPSREG_XR(25)
#define XR54 CHIPSREG_XR(26)
#define XR55 CHIPSREG_XR(27)
#define XR56 CHIPSREG_XR(28)
#define XR57 CHIPSREG_XR(29)
#define XR58 CHIPSREG_XR(30)
#define XR5A CHIPSREG_XR(31)
#define XR64 CHIPSREG_XR(32)
#define XR65 CHIPSREG_XR(33)
#define XR66 CHIPSREG_XR(34)
#define XR67 CHIPSREG_XR(35)
#define XR68 CHIPSREG_XR(36)
#define XR6F CHIPSREG_XR(37)
#define HiQVXR09 CHIPSREG_HiQVXR(0)
#define HiQVXR0A CHIPSREG_HiQVXR(1)
#define HiQVXR0E CHIPSREG_HiQVXR(2)
#define HiQVXR20 CHIPSREG_HiQVXR(3)
#define HiQVXR40 CHIPSREG_HiQVXR(4)
#define HiQVXR80 CHIPSREG_HiQVXR(5)
#define HiQVXR81 CHIPSREG_HiQVXR(6)
#define HiQVXRE2 CHIPSREG_HiQVXR(7)

#define HiQVFR03 CHIPSREG_HiQVFR(0)
#define HiQVFR08 CHIPSREG_HiQVFR(1)
#define HiQVFR10 CHIPSREG_HiQVFR(2)
#define HiQVFR11 CHIPSREG_HiQVFR(3)
#define HiQVFR12 CHIPSREG_HiQVFR(4)
#define HiQVFR20 CHIPSREG_HiQVFR(5)
#define HiQVFR21 CHIPSREG_HiQVFR(6)
#define HiQVFR22 CHIPSREG_HiQVFR(7)
#define HiQVFR23 CHIPSREG_HiQVFR(8)
#define HiQVFR24 CHIPSREG_HiQVFR(9)
#define HiQVFR25 CHIPSREG_HiQVFR(10)
#define HiQVFR26 CHIPSREG_HiQVFR(11)
#define HiQVFR27 CHIPSREG_HiQVFR(12)
#define HiQVFR30 CHIPSREG_HiQVFR(13)
#define HiQVFR31 CHIPSREG_HiQVFR(14)
#define HiQVFR32 CHIPSREG_HiQVFR(15)
#define HiQVFR33 CHIPSREG_HiQVFR(16)
#define HiQVFR34 CHIPSREG_HiQVFR(17)
#define HiQVFR35 CHIPSREG_HiQVFR(18)
#define HiQVFR36 CHIPSREG_HiQVFR(19)
#define HiQVFR37 CHIPSREG_HiQVFR(20)
#define HiQVFR40 CHIPSREG_HiQVFR(21)
#define HiQVFR48 CHIPSREG_HiQVFR(22)
#define HiQVFR73 CHIPSREG_HiQVFR(23)

#define HiQVCR30 CHIPSREG_HiQVCR(0)
#define HiQVCR31 CHIPSREG_HiQVCR(1)
#define HiQVCR32 CHIPSREG_HiQVCR(2)
#define HiQVCR33 CHIPSREG_HiQVCR(3)
#define HiQVCR38 CHIPSREG_HiQVCR(4)
#define HiQVCR3C CHIPSREG_HiQVCR(5)
#define HiQVCR41 CHIPSREG_HiQVCR(6)

/* Define the set of fixed H/W clocks used by those chips that don't
 * support programmable clocks */
#define CHIPS_NUM_CLOCKS 4
static int chips_fixed_clocks[CHIPS_NUM_CLOCKS] =
{
    25175, 28322, 31500, 35500
};
#ifndef CHIPS_PROBE_TEXT_CLOCK
#define LCD_TXT_CLOCK_FREQ 25175
#define CRT_TXT_CLOCK_FREQ 28322
#endif
static int ctTextClock = 0;
static int ctDacSpeed = 0;

static int CHIPS_init(int, int, int);
static int CHIPS_interlaced(int mode);
static void CHIPS_EnterLeave(Bool enter);
static void CHIPS_setlinear(int addr);
static int vgaIOBase = 0;
static Bool ctisHiQV = FALSE;
static Bool PCIcard = FALSE;
static unsigned long chips_pcilinearbase = -1;

#define CT_520	 0
#define CT_525	 1
#define CT_530	 2
#define CT_535	 3