mcf5206e.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define MCF5206E_CSCR_WS14  (0x3800) /* 14 Wait States */
#define MCF5206E_CSCR_WS15  (0x3C00) /* 15 Wait States */
#define MCF5206E_CSCR_BRST  (0x0200) /* Burst Enable */
#define MCF5206E_CSCR_AA    (0x0100) /* Coldfire Core Auto Acknowledge
                                        Enable */
#define MCF5206E_CSCR_PS    (0x00C0) /* Port Size */
#define MCF5206E_CSCR_PS_S  (6)
#define MCF5206E_CSCR_PS_32 (0x0000) /* Port Size = 32 bits */
#define MCF5206E_CSCR_PS_8  (0x0040) /* Port Size = 8 bits */
#define MCF5206E_CSCR_PS_16 (0x0080) /* Port Size = 16 bits */
#define MCF5206E_CSCR_EMAA  (0x0020) /* External Master Automatic Acknowledge
                                        Enable */
#define MCF5206E_CSCR_ASET  (0x0010) /* Address Setup Enable */
#define MCF5206E_CSCR_WRAH  (0x0008) /* Write Address Hold Enable */
#define MCF5206E_CSCR_RDAH  (0x0004) /* Read Address Hold Enable */
#define MCF5206E_CSCR_WR    (0x0002) /* Write Enable */
#define MCF5206E_CSCR_RD    (0x0001) /* Read Enable */

/* Default Memory Control Register */
#define MCF5206E_DMCR(mbar) MCF5206E_REG16(mbar, 0x0C6)

/*** Parallel Port (GPIO) Module -- MCF5206e User's Manual, Chapter 10 ***/

/* Port A Data Direction Register */
#define MCF5206E_PPDDR(mbar) MCF5206E_REG8(mbar,0x1C5)

/* Port A Data Register */
#define MCF5206E_PPDAT(mbar) MCF5206E_REG8(mbar,0x1C9)

#define MCF5206E_PP_DAT0  (0x01)
#define MCF5206E_PP_DAT1  (0x02)
#define MCF5206E_PP_DAT2  (0x04)
#define MCF5206E_PP_DAT3  (0x08)
#define MCF5206E_PP_DAT4  (0x10)
#define MCF5206E_PP_DAT5  (0x20)
#define MCF5206E_PP_DAT6  (0x40)
#define MCF5206E_PP_DAT7  (0x80)

/*** DRAM Controller -- MCF5206e User's Manual, Chapter 11 ***/

/* DRAM Controller Refresh Register */
#define MCF5206E_DCRR(mbar) MCF5206E_REG16(mbar,0x046)

/* DRAM Controller Timing Register */
#define MCF5206E_DCTR(mbar) MCF5206E_REG16(mbar,0x04A)
#define MCF5206E_DCTR_DAEM  (0x8000) /* Drive Multiplexed Address During
                                        External Master DRAM Transfers */
#define MCF5206E_DCTR_EDO   (0x4000) /* Extended Data-Out Enable */
#define MCF5206E_DCTR_RCD   (0x1000) /* RAS-to-CAS Delay Time */
#define MCF5206E_DCTR_RSH   (0x0600) /* RAS Hold Time */
#define MCF5206E_DCTR_RSH_0 (0x0000) /* See User's Manual for details */
#define MCF5206E_DCTR_RSH_1 (0x0200)
#define MCF5206E_DCTR_RSH_2 (0x0400)
#define MCF5206E_DCTR_RP    (0x0060) /* RAS Precharge Time */
#define MCF5206E_DCTR_RP_15 (0x0000) /* RAS Precharges for 1.5 system clks */
#define MCF5206E_DCTR_RP_25 (0x0020) /* RAS Precharges for 2.5 system clks */
#define MCF5206E_DCTR_RP_35 (0x0040) /* RAS Precharges for 3.5 system clks */
#define MCF5206E_DCTR_CAS   (0x0008) /* Column Address Strobe Time */
#define MCF5206E_DCTR_CP    (0x0002) /* CAS Precharge Time */
#define MCF5206E_DCTR_CSR   (0x0001) /* CAS Setup Time for CAS before RAS
                                        refresh */

/* DRAM Controller Address Registers */
#define MCF5206E_DCAR(mbar,bank) MCF5206E_REG16(mbar,0x4C + ((bank) * 12))

/* DRAM Controller Mask Registers */
#define MCF5206E_DCMR(mbar,bank) MCF5206E_REG32(mbar,0x50 + ((bank) * 12))
#define MCF5206E_DCMR_BAM (0xffff0000) /* Base Address Mask */
#define MCF5206E_DCMR_BAM_S (16)
#define MCF5206E_DCMR_MASK_256M  (0x0FFE0000)
#define MCF5206E_DCMR_MASK_128M  (0x07FE0000)
#define MCF5206E_DCMR_MASK_64M   (0x03FE0000)
#define MCF5206E_DCMR_MASK_32M   (0x01FE0000)
#define MCF5206E_DCMR_MASK_16M   (0x00FE0000)
#define MCF5206E_DCMR_MASK_8M    (0x007E0000)
#define MCF5206E_DCMR_MASK_4M    (0x003E0000)
#define MCF5206E_DCMR_MASK_2M    (0x001E0000)
#define MCF5206E_DCMR_MASK_1M    (0x000E0000)
#define MCF5206E_DCMR_MASK_1024K (0x000E0000)
#define MCF5206E_DCMR_MASK_512K  (0x00060000)
#define MCF5206E_DCMR_MASK_256K  (0x00020000)
#define MCF5206E_DCMR_MASK_128K  (0x00000000)
#define MCF5206E_DCMR_SC  (0x00000010) /* Supervisor Code Space Mask */
#define MCF5206E_DCMR_SD  (0x00000008) /* Supervisor Data Space Mask */
#define MCF5206E_DCMR_UC  (0x00000004) /* User Code Space Mask */
#define MCF5206E_DCMR_UD  (0x00000002) /* User Data Space Mask */

/* DRAM Controller Control Register */
#define MCF5206E_DCCR(mbar,bank) MCF5206E_REG8(mbar, 0x57 + ((bank) * 12))
#define MCF5206E_DCCR_PS        (0xC0) /* Port Size */
#define MCF5206E_DCCR_PS_32     (0x00) /* 32 bit Port Size */
#define MCF5206E_DCCR_PS_8      (0x40) /* 8 bit Port Size */
#define MCF5206E_DCCR_PS_16     (0x80) /* 16 bit Port Size */
#define MCF5206E_DCCR_BPS       (0x30) /* Bank Page Size */
#define MCF5206E_DCCR_BPS_512   (0x00) /* 512 Byte Page Size */
#define MCF5206E_DCCR_BPS_1K    (0x10) /* 1 KByte Page Size */
#define MCF5206E_DCCR_BPS_2K    (0x20) /* 2 KByte Page Size */
#define MCF5206E_DCCR_PM        (0x0C) /* Page Mode Select */
#define MCF5206E_DCCR_PM_NORMAL (0x00) /* Normal Mode */
#define MCF5206E_DCCR_PM_BURSTP (0x04) /* Burst Page Mode */
#define MCF5206E_DCCR_PM_FASTP  (0x0C) /* Fast Page Mode */
#define MCF5206E_DCCR_WR        (0x02) /* Write Enable */
#define MCF5206E_DCCR_RD        (0x01) /* Read Enable */

/*** UART Module -- MCF5206e User's Manual, Chapter 12 ***/

#define MCF5206E_UART_CHANNELS (2)
/* UART Mode Register */
#define MCF5206E_UMR(mbar,n) MCF5206E_REG8(mbar,0x140 + (((n)-1) * 0x40))
#define MCF5206E_UMR1_RXRTS          (0x80) /* Receiver Request-to-Send
                                               Control */
#define MCF5206E_UMR1_RXIRQ          (0x40) /* Receiver Interrupt Select */
#define MCF5206E_UMR1_ERR            (0x20) /* Error Mode */
#define MCF5206E_UMR1_PM             (0x1C) /* Parity Mode, Parity Type */
#define MCF5206E_UMR1_PM_EVEN        (0x00) /* Even Parity */
#define MCF5206E_UMR1_PM_ODD         (0x04) /* Odd Parity */
#define MCF5206E_UMR1_PM_FORCE_LOW   (0x08) /* Force parity low */
#define MCF5206E_UMR1_PM_FORCE_HIGH  (0x0C) /* Force parity high */
#define MCF5206E_UMR1_PM_NO_PARITY   (0x10) /* No Parity */
#define MCF5206E_UMR1_PM_MULTI_DATA  (0x18) /* Multidrop mode - data char */
#define MCF5206E_UMR1_PM_MULTI_ADDR  (0x1C) /* Multidrop mode - addr char */
#define MCF5206E_UMR1_BC             (0x03) /* Bits per Character */
#define MCF5206E_UMR1_BC_5           (0x00) /* 5 bits per character */
#define MCF5206E_UMR1_BC_6           (0x01) /* 6 bits per character */
#define MCF5206E_UMR1_BC_7           (0x02) /* 7 bits per character */
#define MCF5206E_UMR1_BC_8           (0x03) /* 8 bits per character */

#define MCF5206E_UMR2_CM             (0xC0) /* Channel Mode */
#define MCF5206E_UMR2_CM_NORMAL      (0x00) /* Normal Mode */
#define MCF5206E_UMR2_CM_AUTO_ECHO   (0x40) /* Automatic Echo Mode */
#define MCF5206E_UMR2_CM_LOCAL_LOOP  (0x80) /* Local Loopback Mode */
#define MCF5206E_UMR2_CM_REMOTE_LOOP (0xC0) /* Remote Loopback Modde */
#define MCF5206E_UMR2_TXRTS          (0x20) /* Transmitter Ready-to-Send op */
#define MCF5206E_UMR2_TXCTS          (0x10) /* Transmitter Clear-to-Send op */
#define MCF5206E_UMR2_SB             (0x0F) /* Stop Bit Length */
#define MCF5206E_UMR2_SB_1           (0x07) /* 1 Stop Bit for 6-8 bits char */
#define MCF5206E_UMR2_SB_15          (0x08) /* 1.5 Stop Bits for 6-8 bits chr*/
#define MCF5206E_UMR2_SB_2           (0x0F) /* 2 Stop Bits for 6-8 bits char */
#define MCF5206E_UMR2_SB5_1          (0x00) /* 1 Stop Bits for 5 bit char */
#define MCF5206E_UMR2_SB5_15         (0x07) /* 1.5 Stop Bits for 5 bit char */
#define MCF5206E_UMR2_SB5_2          (0x0F) /* 2 Stop Bits for 5 bit char */

/* UART Status Register (read only) */
#define MCF5206E_USR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40))
#define MCF5206E_USR_RB     (0x80) /* Received Break */
#define MCF5206E_USR_FE     (0x40) /* Framing Error */
#define MCF5206E_USR_PE     (0x20) /* Parity Error */
#define MCF5206E_USR_OE     (0x10) /* Overrun Error */
#define MCF5206E_USR_TXEMP  (0x08) /* Transmitter Empty */
#define MCF5206E_USR_TXRDY  (0x04) /* Transmitter Ready */
#define MCF5206E_USR_FFULL  (0x02) /* FIFO Full */
#define MCF5206E_USR_RXRDY  (0x01) /* Receiver Ready */

/* UART Clock Select Register (write only) */
#define MCF5206E_UCSR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40))
#define MCF5206E_UCSR_RCS       (0xF0) /* Receiver Clock Select */
#define MCF5206E_UCSR_RCS_TIMER (0xD0) /* Timer */
#define MCF5206E_UCSR_RCS_EXT16 (0xE0) /* External clk x16 */
#define MCF5206E_UCSR_RCS_EXT   (0xF0) /* External clk x1 */
#define MCF5206E_UCSR_TCS       (0x0F) /* Transmitter Clock Select */
#define MCF5206E_UCSR_TCS_TIMER (0x0D) /* Timer */
#define MCF5206E_UCSR_TCS_EXT16 (0x0E) /* External clk x16 */
#define MCF5206E_UCSR_TCS_EXT   (0x0F) /* External clk x1 */

/* UART Command Register (write only) */
#define MCF5206E_UCR(mbar,n) MCF5206E_REG8(mbar,0x148 + (((n)-1) * 0x40))
#define MCF5206E_UCR_MISC            (0x70) /* Miscellaneous Commands: */
#define MCF5206E_UCR_MISC_NOP        (0x00) /* No Command */
#define MCF5206E_UCR_MISC_RESET_MR   (0x10) /* Reset Mode Register Ptr */
#define MCF5206E_UCR_MISC_RESET_RX   (0x20) /* Reset Receiver */
#define MCF5206E_UCR_MISC_RESET_TX   (0x30) /* Reset Transmitter */
#define MCF5206E_UCR_MISC_RESET_ERR  (0x40) /* Reset Error Status */
#define MCF5206E_UCR_MISC_RESET_BRK  (0x50) /* Reset Break-Change Interrupt */
#define MCF5206E_UCR_MISC_START_BRK  (0x60) /* Start Break */
#define MCF5206E_UCR_MISC_STOP_BRK   (0x70) /* Stop Break */
#define MCF5206E_UCR_TC              (0x0C) /* Transmitter Commands: */
#define MCF5206E_UCR_TC_NOP          (0x00) /* No Action Taken */
#define MCF5206E_UCR_TC_ENABLE       (0x04) /* Transmitter Enable */
#define MCF5206E_UCR_TC_DISABLE      (0x08) /* Transmitter Disable */
#define MCF5206E_UCR_RC              (0x03) /* Receiver Commands: */
#define MCF5206E_UCR_RC_NOP          (0x00) /* No Action Taken */
#define MCF5206E_UCR_RC_ENABLE       (0x01) /* Receiver Enable */
#define MCF5206E_UCR_RC_DISABLE      (0x02) /* Receiver Disable */

/* UART Receive Buffer (read only) */
#define MCF5206E_URB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40))

/* UART Transmit Buffer (write only) */
#define MCF5206E_UTB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40))

/* UART Input Port Change Register (read only) */
#define MCF5206E_UIPCR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40))
#define MCF5206E_UIPCR_COS   (0x10) /* Change of State at CTS input */
#define MCF5206E_UIPCR_CTS   (0x01) /* Current State of CTS */

/* UART Auxiliary Control Register (write only) */
#define MCF5206E_UACR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40))
#define MCF5206E_UACR_IEC (0x01) /* Input Enable Control - generate interrupt
                                    on CTS change */

/* UART Interrupt Status Register (read only) */
#define MCF5206E_UISR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40))
#define MCF5206E_UISR_COS   (0x80) /* Change of State has occured at CTS */
#define MCF5206E_UISR_DB    (0x04) /* Delta Break */
#define MCF5206E_UISR_RXRDY (0x02) /* Receiver Ready or FIFO Full */
#define MCF5206E_UISR_TXRDY (0x01) /* Transmitter Ready */

/* UART Interrupt Mask Register (write only) */
#define MCF5206E_UIMR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40))
#define MCF5206E_UIMR_COS   (0x80) /* Change of State interrupt enable */
#define MCF5206E_UIMR_DB    (0x04) /* Delta Break interrupt enable */
#define MCF5206E_UIMR_FFULL (0x02) /* FIFO Full interrupt enable */
#define MCF5206E_UIMR_TXRDY (0x01) /* Transmitter Ready Interrupt enable */

/* UART Baud Rate Generator Prescale MSB Register */
#define MCF5206E_UBG1(mbar,n) MCF5206E_REG8(mbar,0x158 + (((n)-1) * 0x40))

/* UART Baud Rate Generator Prescale LSB Register */
#define MCF5206E_UBG2(mbar,n) MCF5206E_REG8(mbar,0x15C + (((n)-1) * 0x40))

/* UART Interrupt Vector Register */
#define MCF5206E_UIVR(mbar,n) MCF5206E_REG8(mbar,0x170 + (((n)-1) * 0x40))

/* UART Input Port Register (read only) */
#define MCF5206E_UIP(mbar,n) MCF5206E_REG8(mbar,0x174 + (((n)-1) * 0x40))
#define MCF5206E_UIP_CTS  (0x01) /* Current state of CTS input */

/* UART Output Port Bit Set Command (address-triggered command, write) */
#define MCF5206E_UOP1(mbar,n) MCF5206E_REG8(mbar,0x178 + (((n)-1) * 0x40))

/* UART Output Port Bit Reset Command (address-triggered command, write */
#define MCF5206E_UOP0(mbar,n) MCF5206E_REG8(mbar,0x17C + (((n)-1) * 0x40))

/*** M-BUS (I2C) Module -- MCF5206e User's Manual, Chapter 13 ***/

/* M-Bus Address Register */
#define MCF5206E_MADR(mbar) MCF5206E_REG8(mbar, 0x1E0)

/* M-Bus Frequency Divider Register */
#define MCF5206E_MFDR(mbar) MCF5206E_REG8(mbar, 0x1E4)

/* M-Bus Control Register */
#define MCF5206E_MBCR(mbar) MCF5206E_REG8(mbar, 0x1E8)
#define MCF5206E_MBCR_MEN    (0x80) /* M-Bus Enable */
#define MCF5206E_MBCR_MIEN   (0x40) /* M-Bus Interrupt Enable */
#define MCF5206E_MBCR_MSTA   (0x20) /* Master Mode Selection */
#define MCF5206E_MBCR_MTX    (0x10) /* Transmit Mode Selection */
#define MCF5206E_MBCR_TXAK   (0x08) /* Transmit Acknowledge Enable */
#define MCF5206E_MBCR_RSTA   (0x04) /* Repeat Start */

/* M-Bus Status Register */
#define MCF5206E_MBSR(mbar) MCF5206E_REG8(mbar, 0x1EC)
#define MCF5206E_MBSR_MCF    (0x80) /* Data Transferring Bit */
#define MCF5206E_MBSR_MAAS   (0x40) /* Addressed as a Slave Bit */
#define MCF5206E_MBSR_MBB    (0x20) /* Bus Busy Bit */
#define MCF5206E_MBSR_MAL    (0x10) /* Arbitration Lost */
#define MCF5206E_MBSR_SRW    (0x04) /* Slave Read/Write */
#define MCF5206E_MBSR_MIF    (0x02) /* MBus Interrupt pending */
#define MCF5206E_MBSR_RXAK   (0x01) /* Received Acknowledge */

/* M-Bus Data I/O Register */
#define MCF5206E_MBDR(mbar) MCF5206E_REG8(mbar, 0x1F0)

/*** Timer Module -- MCF5206e User's Manual, Chapter 14 ***/

/* Timer Mode Register */
#define MCF5206E_TMR(mbar,n) MCF5206E_REG16(mbar, 0x100 + (((n)-1)*0x20))
#define MCF5206E_TMR_PS          (0xFF00) /* Prescaler Value */
#define MCF5206E_TMR_PS_S        (8)
#define MCF5206E_TMR_CE          (0x00C0) /* Capture Edge and Enable
                                             Interrupt */
#define MCF5206E_TMR_CE_ANY      (0x00C0) /* Capture on any edge */
#define MCF5206E_TMR_CE_FALL     (0x0080) /* Capture on falling edge only */
#define MCF5206E_TMR_CE_RISE     (0x0040) /* Capture on rising edge only */
#define MCF5206E_TMR_CE_NONE     (0x0000) /* Disable Interrupt on capture
                                             event */
#define MCF5206E_TMR_OM          (0x0020) /* Output Mode - Toggle output */
#define MCF5206E_TMR_ORI         (0x0010) /* Output Reference Interrupt 
                                             Enable */
#define MCF5206E_TMR_FRR         (0x0008) /* Free Run/Restart */
#define MCF5206E_TMR_ICLK        (0x0006) /* Input Clock Source */
#define MCF5206E_TMR_ICLK_TIN    (0x0006) /* TIN pin (falling edge) */
#define MCF5206E_TMR_ICLK_DIV16  (0x0004) /* Master system clock divided
                                             by 16 */
#define MCF5206E_TMR_ICLK_MSCLK  (0x0002) /* Master System Clock */
#define MCF5206E_TMR_ICLK_STOP   (0x0000) /* Stops counter */
#define MCF5206E_TMR_RST         (0x0001) /* Reset/Enable Timer */

/* Timer Reference Register */
#define MCF5206E_TRR(mbar,n) MCF5206E_REG16(mbar, 0x104 + (((n)-1)*0x20))

/* Timer Capture Register */
#define MCF5206E_TCR(mbar,n) MCF5206E_REG16(mbar, 0x108 + (((n)-1)*0x20))

/* Timer Counter Register */
#define MCF5206E_TCN(mbar,n) MCF5206E_REG16(mbar, 0x10C + (((n)-1)*0x20))

/* Timer Event Register */
#define MCF5206E_TER(mbar,n) MCF5206E_REG8(mbar, 0x111 + (((n)-1)*0x20))
#define MCF5206E_TER_REF  (0x02) /* Output Reference Event */
#define MCF5206E_TER_CAP  (0x01) /* Capture Event */



#endif