mcf5206e.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*
 * Coldfire MCF5206e on-chip peripherial definitions.
 * Contents of this file based on information provided in
 * Motorola MCF5206e User's Manual
 *
 * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
 * Author: Victor V. Vengerov <[e-mail]>
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 *
 * http://www.rtems.com/license/LICENSE.
 *
 * @(#) $Id: mcf5206e.h,v 1.1.4.1 2003/09/04 18:45:44 joel Exp $
 */

#ifndef __MCF5206E_H__
#define __MCF5206E_H__

#ifdef ASM
#define MCF5206E_REG8(base,ofs) (ofs+base)
#define MCF5206E_REG16(base,ofs) (ofs+base)
#define MCF5206E_REG32(base,ofs) (ofs+base)
#else
#define MCF5206E_REG8(base,ofs) \
    (volatile rtems_unsigned8 *)((rtems_unsigned8 *)(base) + (ofs))
#define MCF5206E_REG16(base,ofs) \
    (volatile rtems_unsigned16 *)((rtems_unsigned8 *)(base) + (ofs))
#define MCF5206E_REG32(base,ofs) \
    (volatile rtems_unsigned32 *)((rtems_unsigned8 *)(base) + (ofs))
#endif

/*** Instruction Cache -- MCF5206e User's Manual, Chapter 4 ***/

/* CACR - Cache Control Register */
#define MCF5206E_CACR_CENB  (0x80000000) /* Cache Enable */
#define MCF5206E_CACR_CPDI  (0x10000000) /* Disable CPUSHL Invalidation */
#define MCF5206E_CACR_CFRZ  (0x08000000) /* Cache Freeze */
#define MCF5206E_CACR_CINV  (0x01000000) /* Cache Invalidate */
#define MCF5206E_CACR_CEIB  (0x00000400) /* Cache Enable Noncacheable
                                            instruction bursting */
#define MCF5206E_CACR_DCM   (0x00000200) /* Default cache mode - noncacheable*/
#define MCF5206E_CACR_DBWE  (0x00000100) /* Default Buffered Write Enable */
#define MCF5206E_CACR_DWP   (0x00000020) /* Default Write Protection */
#define MCF5206E_CACR_CLNF  (0x00000003) /* Cache Line Fill */

/* ACR0, ACR1 - Access Control Registers */
#define MCF5206E_ACR_AB     (0xff000000) /* Address Base */
#define MCF5206E_ACR_AB_S   (24)
#define MCF5206E_ACR_AM     (0x00ff0000) /* Address Mask */
#define MCF5206E_ACR_AM_S   (16)
#define MCF5206E_ACR_EN     (0x00008000) /* Enable ACR */
#define MCF5206E_ACR_SM     (0x00006000) /* Supervisor Mode */
#define MCF5206E_ACR_SM_USR (0x00000000) /* Match if user mode */
#define MCF5206E_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */
#define MCF5206E_ACR_SM_ANY (0x00004000) /* Match Always */
#define MCF5206E_ACR_CM     (0x00000040) /* Cache Mode (1 - noncacheable) */
#define MCF5206E_ACR_BUFW   (0x00000020) /* Buffered Write Enable */
#define MCF5206E_ACR_WP     (0x00000004) /* Write Protect */
#define MCF5206E_ACR_BASE(base) ((base) & MCF5206E_ACR_AB)
#define MCF5206E_ACR_MASK(mask) (((mask) >> 8) & MCF5206E_ACR_AM)

/*** SRAM -- MCF5206e User's Manual, Chapter 5 ***/

/* RAMBAR - SRAM Base Address Register */
#define MCF5206E_RAMBAR_BA  (0xffffe000) /* SRAM Base Address */
#define MCF5206E_RAMBAR_WP  (0x00000100) /* Write Protect */
#define MCF5206E_RAMBAR_CI  (0x00000020) /* CPU Space mask */
#define MCF5206E_RAMBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
#define MCF5206E_RAMBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
#define MCF5206E_RAMBAR_UC  (0x00000004) /* User Code Space Mask */
#define MCF5206E_RAMBAR_UD  (0x00000002) /* User Data Space Mask */
#define MCF5206E_RAMBAR_V   (0x00000001) /* Contents of RAMBAR are valid */

/*** DMA Controller Module -- MCF5206e User's Manual, Chapter 7 ***/

/* DMA Source Address Register */
#define MCF5206E_SAR(mbar,chn) MCF5206E_REG32(mbar,0x200 + ((chn) * 0x40))

/* DMA Destination Address Register */
#define MCF5206E_DAR(mbar,chn) MCF5206E_REG32(mbar,0x204 + ((chn) * 0x40))

/* DMA Byte Count Register */
#define MCF5206E_BCR(mbar,chn) MCF5206E_REG16(mbar,0x20C + ((chn) * 0x40))

/* DMA Control Register */
#define MCF5206E_DCR(mbar,chn) MCF5206E_REG16(mbar,0x208 + ((chn) * 0x40))
#define MCF5206E_DCR_INT    (0x8000) /* Interrupt on completion of transfer */
#define MCF5206E_DCR_EEXT   (0x4000) /* Enable External DMA Request */
#define MCF5206E_DCR_CS     (0x2000) /* Cycle Steal */
#define MCF5206E_DCR_AA     (0x1000) /* Auto Align */
#define MCF5206E_DCR_BWC    (0x0E00) /* Bandwidth Control: */
#define MCF5206E_DCR_BWC_DISABLE (0x0000) /* Bandwidth Control Disabled */
#define MCF5206E_DCR_BWC_512     (0x0200) /* 512 bytes */
#define MCF5206E_DCR_BWC_1024    (0x0400) /* 1024 bytes */
#define MCF5206E_DCR_BWC_2048    (0x0600) /* 2048 bytes */
#define MCF5206E_DCR_BWC_4096    (0x0800) /* 4096 bytes */
#define MCF5206E_DCR_BWC_8192    (0x0A00) /* 8192 bytes */
#define MCF5206E_DCR_BWC_16384   (0x0C00) /* 16384 bytes */
#define MCF5206E_DCR_BWC_32768   (0x0E00) /* 32768 bytes */
#define MCF5206E_DCR_SAA    (0x0100) /* Single Address Access */
#define MCF5206E_DCR_S_RW   (0x0080) /* Single Address Access Read/Write Val */
#define MCF5206E_DCR_SINC   (0x0040) /* Source Increment */
#define MCF5206E_DCR_SSIZE  (0x0030) /* Source Size: */
#define MCF5206E_DCR_SSIZE_LONG  (0x0000) /* Longword (4 bytes) */
#define MCF5206E_DCR_SSIZE_BYTE  (0x0010) /* Byte */
#define MCF5206E_DCR_SSIZE_WORD  (0x0020) /* Word (2 bytes) */
#define MCF5206E_DCR_SSIZE_LINE  (0x0030) /* Line (16 bytes) */
#define MCF5206E_DCR_DINC   (0x0008) /* Destination Increment */
#define MCF5206E_DCR_DSIZE  (0x0006) /* Destination Size: */
#define MCF5206E_DCR_DSIZE_LONG  (0x0000) /* Longword (4 bytes) */
#define MCF5206E_DCR_DSIZE_BYTE  (0x0002) /* Byte */
#define MCF5206E_DCR_DSIZE_WORD  (0x0004) /* Word (2 bytes) */
#define MCF5206E_DCR_DSIZE_LINE  (0x0006) /* Line (16 bytes) */
#define MCF5206E_DCR_START  (0x0001) /* Start Transfer */

/* DMA Status Register */
#define MCF5206E_DSR(mbar,chn) MCF5206E_REG8(mbar,0x210 + ((chn) * 0x40))
#define MCF5206E_DSR_CE     (0x40) /* Configuration Error has occured */
#define MCF5206E_DSR_BES    (0x20) /* Bus Error on Source */
#define MCF5206E_DSR_BED    (0x10) /* Bus Error on Destination */
#define MCF5206E_DSR_REQ    (0x04) /* Request */
#define MCF5206E_DSR_BSY    (0x02) /* Busy */
#define MCF5206E_DSR_DONE   (0x01) /* Transaction Done */

/* DMA Interrupt Vector Register */
#define MCF5206E_DIVR(mbar,chn) MCF5206E_REG8(mbar,0x214 + ((chn) * 0x40))


/*** System Integration Module -- MCF5206e User's Manual, Chapter 8 ***/

/* MBAR - Module Base Address Register */
#define MCF5206E_MBAR_BA  (0xFFFFFC00) /* Base Address */
#define MCF5206E_MBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
#define MCF5206E_MBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
#define MCF5206E_MBAR_UC  (0x00000004) /* User Code Space Mask */
#define MCF5206E_MBAR_UD  (0x00000002) /* User Data Space Mask */
#define MCF5206E_MBAR_V   (0x00000001) /* Contents of MBAR are valid */

/* SIM Configuration Register */
#define MCF5206E_SIMR(mbar) MCF5206E_REG8(mbar,0x003)
#define MCF5206E_SIMR_FRZ1 (0x80)  /* Disable Soft Wdog Timer when FREEZE */
#define MCF5206E_SIMR_FRZ0 (0x40)  /* Disable Bus Timeout monitor when FREEZE*/
#define MCF5206E_SIMR_BL   (0x01)  /* Bus Lock Enable */

/* Interrupt numbers assignment */
#define MCF5206E_INTR_EXT_IRQ1 (1)   /* External IRQ1 */
#define MCF5206E_INTR_EXT_IPL1 (1)   /* External IPL1 */
#define MCF5206E_INTR_EXT_IPL2 (2)   /* External IPL2 */
#define MCF5206E_INTR_EXT_IPL3 (3)   /* External IPL3 */
#define MCF5206E_INTR_EXT_IRQ4 (4)   /* External IRQ4 */
#define MCF5206E_INTR_EXT_IPL4 (4)   /* External IPL4 */
#define MCF5206E_INTR_EXT_IPL5 (5)   /* External IPL5 */
#define MCF5206E_INTR_EXT_IPL6 (6)   /* External IPL6 */
#define MCF5206E_INTR_EXT_IRQ7 (7)   /* External IRQ7 */
#define MCF5206E_INTR_EXT_IPL7 (7)   /* External IPL7 */
#define MCF5206E_INTR_SWT      (8)   /* Software Watchdog Timer */
#define MCF5206E_INTR_TIMER_1  (9)   /* Timer 1 interrupt */
#define MCF5206E_INTR_TIMER_2  (10)  /* Timer 2 interrupt */
#define MCF5206E_INTR_MBUS     (11)  /* MBUS interrupt */
#define MCF5206E_INTR_UART_1   (12)  /* UART 1 interrupt */
#define MCF5206E_INTR_UART_2   (13)  /* UART 2 interrupt */
#define MCF5206E_INTR_DMA_0    (14)  /* DMA channel 0 interrupt */
#define MCF5206E_INTR_DMA_1    (15)  /* DMA channel 1 interrupt */

#define MCF5206E_INTR_BIT(n) (1 << (n))

/* Interrupt Control Registers (ICR1 - ICR15) */
#define MCF5206E_ICR(mbar,n) MCF5206E_REG8(mbar,0x014 + (n) - 1)

#define MCF5206E_ICR_AVEC (0x80) /* Autovector Enable */
#define MCF5206E_ICR_IL   (0x1c) /* Interrupt Level */
#define MCF5206E_ICR_IL_S (2)
#define MCF5206E_ICR_IP   (0x03) /* Interrupt Priority */
#define MCF5206E_ICR_IP_S (0)

/* Interrupt Mask Register */
#define MCF5206E_IMR(mbar) MCF5206E_REG16(mbar,0x036)

/* Interrupt Pending Register */
#define MCF5206E_IPR(mbar) MCF5206E_REG16(mbar,0x03a)

/* Reset Status Register */
#define MCF5206E_RSR(mbar) MCF5206E_REG8(mbar,0x040)
#define MCF5206E_RSR_HRST  (0x80) /* Hard Reset or System Reset */
#define MCF5206E_RSR_SWTR  (0x20) /* Software Watchdog Timer Reset */

/* System Protection Control Register */
#define MCF5206E_SYPCR(mbar) MCF5206E_REG8(mbar,0x041)
#define MCF5206E_SYPCR_SWE   (0x80) /* Software Watchdog Enable */
#define MCF5206E_SYPCR_SWRI  (0x40) /* Software Watchdog Reset/Interrupt Sel.*/
#define MCF5206E_SYPCR_SWP   (0x20) /* Software Watchdog Prescaler */
#define MCF5206E_SYPCR_SWT   (0x18) /* Software Watchdog Timing: */
#define MCF5206E_SYPCR_SWT_S (3)
#define MCF5206E_SYPCR_SWT_9   (0x00) /* timeout = (1<<9)/sysfreq */
#define MCF5206E_SYPCR_SWT_11  (0x08) /* timeout = (1<<11)/sysfreq */
#define MCF5206E_SYPCR_SWT_13  (0x10) /* timeout = (1<<13)/sysfreq */
#define MCF5206E_SYPCR_SWT_15  (0x18) /* timeout = (1<<15)/sysfreq */
#define MCF5206E_SYPCR_SWT_18  (0x20) /* timeout = (1<<18)/sysfreq */
#define MCF5206E_SYPCR_SWT_20  (0x28) /* timeout = (1<<20)/sysfreq */
#define MCF5206E_SYPCR_SWT_22  (0x30) /* timeout = (1<<22)/sysfreq */
#define MCF5206E_SYPCR_SWT_24  (0x38) /* timeout = (1<<24)/sysfreq */
#define MCF5206E_SYPCR_BME   (0x04) /* Bus Timeout Monitor Enable */
#define MCF5206E_SYPCR_BMT   (0x03) /* Bus Monitor Timing: */
#define MCF5206E_SYPCR_BMT_1024 (0x00) /* timeout 1024 system clocks */
#define MCF5206E_SYPCR_BMT_512  (0x01) /* timeout 512 system clocks */
#define MCF5206E_SYPCR_BMT_256  (0x02) /* timeout 256 system clocks */
#define MCF5206E_SYPCR_BMT_128  (0x03) /* timeout 128 system clocks */

/* Software Watchdog Interrupt Vector Register */
#define MCF5206E_SWIVR(mbar) MCF5206E_REG8(mbar,0x042)

/* Software Watchdog Service Register */
#define MCF5206E_SWSR(mbar)  MCF5206E_REG8(mbar,0x043)
#define MCF5206E_SWSR_KEY1 (0x55)
#define MCF5206E_SWSR_KEY2 (0xAA)

/* Pin Assignment Register */
#define MCF5206E_PAR(mbar) MCF5206E_REG16(mbar,0x0CA)
#define MCF5206E_PAR_PAR9          (0x200)
#define MCF5206E_PAR_PAR9_TOUT     (0x000) /* Timer 0 output */
#define MCF5206E_PAR_PAR9_DREQ1    (0x200) /* DMA channel 1 request */
#define MCF5206E_PAR_PAR8          (0x100)
#define MCF5206E_PAR_PAR8_TIN0     (0x000) /* Timer 1 input */
#define MCF5206E_PAR_PAR8_DREQ0    (0x100) /* DMA channel 0 request */
#define MCF5206E_PAR_PAR7          (0x080)
#define MCF5206E_PAR_PAR7_RSTO     (0x000) /* Reset output */
#define MCF5206E_PAR_PAR7_UART2    (0x080) /* UART 2 RTS output */
#define MCF5206E_PAR_PAR6          (0x040)
#define MCF5206E_PAR_PAR6_IRQ      (0x000) /* IRQ7, IRQ4, IRQ1 */
#define MCF5206E_PAR_PAR6_IPL      (0x040) /* IPL2, IPL1, IPL0 */
#define MCF5206E_PAR_PAR5          (0x020)
#define MCF5206E_PAR_PAR5_GPIO     (0x000) /* General purpose I/O PP7-PP4 */
#define MCF5206E_PAR_PAR5_PST      (0x020) /* BDM signals PST3-PST0 */
#define MCF5206E_PAR_PAR4          (0x010)
#define MCF5206E_PAR_PAR4_GPIO     (0x000) /* General purpose I/O PP3-PP0 */
#define MCF5206E_PAR_PAR4_DDATA    (0x010) /* BDM signals DDATA3-DDATA0 */
#define MCF5206E_PAR_PAR3          (0x008)
#define MCF5206E_PAR_PAR2          (0x004)
#define MCF5206E_PAR_PAR1          (0x002)
#define MCF5206E_PAR_PAR0          (0x001)
#define MCF5206E_PAR_WE0_WE1_WE2_WE3 (0x000)
#define MCF5206E_PAR_WE0_WE1_CS5_CS4 (0x001)
#define MCF5206E_PAR_WE0_WE1_CS5_A24 (0x002)
#define MCF5206E_PAR_WE0_WE1_A25_A24 (0x003)
#define MCF5206E_PAR_WE0_CS6_CS5_CS4 (0x004)
#define MCF5206E_PAR_WE0_CS6_CS5_A24 (0x005)
#define MCF5206E_PAR_WE0_CS6_A25_A24 (0x006)
#define MCF5206E_PAR_WE0_A26_A25_A24 (0x007)
#define MCF5206E_PAR_CS7_CS6_CS5_CS4 (0x008)
#define MCF5206E_PAR_CS7_CS6_CS4_A24 (0x009)
#define MCF5206E_PAR_CS7_CS6_A25_A24 (0x00A)
#define MCF5206E_PAR_CS7_A26_A25_A24 (0x00B)
#define MCF5206E_PAR_A27_A26_A25_A24 (0x00C)

/* Bus Master Arbitration Control */
#define MCF5206E_MARB(mbar) MCF5206E_REG8(mbar,0x007)
#define MCF5206E_MARB_NOARB     (0x08) /* Arbiter operation disable */
#define MCF5206E_MARB_ARBCTRL   (0x04) /* Arb. order: Internal DMA, Coldfire */

/*** Chip Select Module -- MCF5206e User's Manual, Chapter 9 ***/

/* Chip Select Address Register */
#define MCF5206E_CSAR(mbar,bank) MCF5206E_REG16(mbar,0x064 + ((bank) * 12))

/* Chip Select Mask Register */
#define MCF5206E_CSMR(mbar,bank) MCF5206E_REG32(mbar,0x068 + ((bank) * 12))
#define MCF5206E_CSMR_BAM (0xffff0000) /* Base Address Mask */
#define MCF5206E_CSMR_BAM_S (16)
#define MCF5206E_CSMR_MASK_256M  (0x0FFF0000)
#define MCF5206E_CSMR_MASK_128M  (0x07FF0000)
#define MCF5206E_CSMR_MASK_64M   (0x03FF0000)
#define MCF5206E_CSMR_MASK_32M   (0x01FF0000)
#define MCF5206E_CSMR_MASK_16M   (0x00FF0000)
#define MCF5206E_CSMR_MASK_8M    (0x007F0000)
#define MCF5206E_CSMR_MASK_4M    (0x003F0000)
#define MCF5206E_CSMR_MASK_2M    (0x001F0000)
#define MCF5206E_CSMR_MASK_1M    (0x000F0000)
#define MCF5206E_CSMR_MASK_1024K (0x000F0000)
#define MCF5206E_CSMR_MASK_512K  (0x00070000)
#define MCF5206E_CSMR_MASK_256K  (0x00030000)
#define MCF5206E_CSMR_MASK_128K  (0x00010000)
#define MCF5206E_CSMR_MASK_64K   (0x00000000)
#define MCF5206E_CSMR_CI  (0x00000020) /* CPU Space Mask (CSMR1 only) */
#define MCF5206E_CSMR_SC  (0x00000010) /* Supervisor Code Space Mask */
#define MCF5206E_CSMR_SD  (0x00000008) /* Supervisor Data Space Mask */
#define MCF5206E_CSMR_UC  (0x00000004) /* User Code Space Mask */
#define MCF5206E_CSMR_UD  (0x00000002) /* User Data Space Mask */

/* Chip Select Control Register */
#define MCF5206E_CSCR(mbar,bank) MCF5206E_REG16(mbar,0x6E + ((bank) * 12))
#define MCF5206E_CSCR_WS    (0x3c00) /* Wait States */
#define MCF5206E_CSCR_WS_S  (10)
#define MCF5206E_CSCR_WS0   (0x0000) /* 0 Wait States */
#define MCF5206E_CSCR_WS1   (0x0400) /* 1 Wait States */
#define MCF5206E_CSCR_WS2   (0x0800) /* 2 Wait States */
#define MCF5206E_CSCR_WS3   (0x0C00) /* 3 Wait States */
#define MCF5206E_CSCR_WS4   (0x1000) /* 4 Wait States */
#define MCF5206E_CSCR_WS5   (0x1400) /* 5 Wait States */
#define MCF5206E_CSCR_WS6   (0x1800) /* 6 Wait States */
#define MCF5206E_CSCR_WS7   (0x1C00) /* 7 Wait States */
#define MCF5206E_CSCR_WS8   (0x2000) /* 8 Wait States */
#define MCF5206E_CSCR_WS9   (0x2400) /* 9 Wait States */
#define MCF5206E_CSCR_WS10  (0x2800) /* 10 Wait States */
#define MCF5206E_CSCR_WS11  (0x2C00) /* 11 Wait States */
#define MCF5206E_CSCR_WS12  (0x3000) /* 12 Wait States */
#define MCF5206E_CSCR_WS13  (0x3400) /* 13 Wait States */