console-generic.c

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

  if (m8260.scc1.scce & M8260_SCCE_TX) {
    m8260.scc1.scce = M8260_SCCE_TX;  /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SCC1_MINOR]->status & M8260_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SCC1_MINOR],
        (int)TxBd[SCC1_MINOR]->length);
  }

#if 0
  m8260.sipnr_l |= M8260_SIMASK_SCC1;      /* Clear pending register */
#endif
}

static void
m8xx_scc2_interrupt_handler ()
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if ((m8260.scc2.sccm & M8260_SCCE_RX) && (m8260.scc2.scce & M8260_SCCE_RX)) {
    m8260.scc2.scce = M8260_SCCE_RX;    /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SCC2_MINOR]->status & M8260_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SCC2_MINOR]->buffer, 
        RxBd[SCC2_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SCC2_MINOR],
        (char *)RxBd[SCC2_MINOR]->buffer,
        (int)RxBd[SCC2_MINOR]->length );
      RxBd[SCC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP |
                                 M8260_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8260.scc2.scce & M8260_SCCE_TX) {
    m8260.scc2.scce = M8260_SCCE_TX;  /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SCC2_MINOR]->status & M8260_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SCC2_MINOR],
        (int)TxBd[SCC2_MINOR]->length);
  }

#if 0
  m8260.sipnr_l |= M8260_SIMASK_SCC2;      /* Clear pending register */
#endif
}


static void
m8xx_scc3_interrupt_handler ()
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if ((m8260.scc3.sccm & M8260_SCCE_RX) && (m8260.scc3.scce & M8260_SCCE_RX)) {
    m8260.scc3.scce = M8260_SCCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SCC3_MINOR]->status & M8260_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SCC3_MINOR]->buffer, 
        RxBd[SCC3_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SCC3_MINOR],
        (char *)RxBd[SCC3_MINOR]->buffer,
        (int)RxBd[SCC3_MINOR]->length );
      RxBd[SCC3_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP |
                                 M8260_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8260.scc3.scce & M8260_SCCE_TX) {
    m8260.scc3.scce = M8260_SCCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SCC3_MINOR]->status & M8260_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SCC3_MINOR],
        (int)TxBd[SCC3_MINOR]->length);
  }


#if 0
  m8260.sipnr_l |= M8260_SIMASK_SCC3;      /* Clear pending register */
#endif
}


static void
m8xx_scc4_interrupt_handler ()
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if ((m8260.scc4.sccm & M8260_SCCE_RX) && (m8260.scc4.scce & M8260_SCCE_RX)) {
    m8260.scc4.scce = M8260_SCCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SCC4_MINOR]->status & M8260_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SCC4_MINOR]->buffer, 
        RxBd[SCC4_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SCC4_MINOR],
        (char *)RxBd[SCC4_MINOR]->buffer,
        (int)RxBd[SCC4_MINOR]->length );
      RxBd[SCC4_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP |
                                 M8260_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8260.scc4.scce & M8260_SCCE_TX) {
    m8260.scc4.scce = M8260_SCCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SCC4_MINOR]->status & M8260_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SCC4_MINOR],
        (int)TxBd[SCC4_MINOR]->length);
  }

#if 0
  m8260.sipnr_l |= M8260_SIMASK_SCC4;      /* Clear pending register */
#endif
}

static void
m8xx_smc1_interrupt_handler ()
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if (m8260.smc1.smce & M8260_SMCE_RX) {
    m8260.smc1.smce = M8260_SMCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SMC1_MINOR]->status & M8260_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SMC1_MINOR]->buffer, 
        RxBd[SMC1_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SMC1_MINOR],
        (char *)RxBd[SMC1_MINOR]->buffer,
        (int)RxBd[SMC1_MINOR]->length );
      RxBd[SMC1_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP |
                                 M8260_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8260.smc1.smce & M8260_SMCE_TX) {
    m8260.smc1.smce = M8260_SMCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SMC1_MINOR]->status & M8260_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SMC1_MINOR],
        (int)TxBd[SMC1_MINOR]->length);
  }

#if 0
  m8260.sipnr_l = 0x00001000; /* Clear SMC1 interrupt-in-service bit */
#endif
}


static void
m8xx_smc2_interrupt_handler ()
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if (m8260.smc2.smce & M8260_SMCE_RX) {
    m8260.smc2.smce = M8260_SMCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SMC2_MINOR]->status & M8260_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SMC2_MINOR]->buffer, 
        RxBd[SMC2_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SMC2_MINOR],
        (char *)RxBd[SMC2_MINOR]->buffer,
        (int)RxBd[SMC2_MINOR]->length );
      RxBd[SMC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP |
                                 M8260_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8260.smc2.smce & M8260_SMCE_TX) {
    m8260.smc2.smce = M8260_SMCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SMC2_MINOR]->status & M8260_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SMC2_MINOR],
        (int)TxBd[SMC2_MINOR]->length);
  }

#if 0
  m8260.sipnr_l = 0x00000800; /* Clear SMC2 interrupt-in-service bit */
#endif
}


void m8xx_scc_enable(const rtems_irq_connect_data* ptr)
{
  volatile m8260SCCRegisters_t *sccregs = 0;
  switch (ptr->name) {
  case BSP_CPM_IRQ_SCC4 :
    m8260.sipnr_l |= M8260_SIMASK_SCC4;
    sccregs = &m8260.scc4;
    break;
  case BSP_CPM_IRQ_SCC3 :
    m8260.sipnr_l |= M8260_SIMASK_SCC3;
    sccregs = &m8260.scc3;
    break;
  case BSP_CPM_IRQ_SCC2 :
    m8260.sipnr_l |= M8260_SIMASK_SCC2;
    sccregs = &m8260.scc2;
    break;
  case BSP_CPM_IRQ_SCC1 :
    m8260.sipnr_l |= M8260_SIMASK_SCC1;
    sccregs = &m8260.scc1;
    break;
  default:
    break;
  }
  sccregs->sccm = 3;
}

void m8xx_scc_disable(const rtems_irq_connect_data* ptr)
{
  volatile m8260SCCRegisters_t *sccregs = 0;
  switch (ptr->name) {
  case BSP_CPM_IRQ_SCC4 :
    sccregs = &m8260.scc4;
    break;
  case BSP_CPM_IRQ_SCC3 :
    sccregs = &m8260.scc3;
    break;
  case BSP_CPM_IRQ_SCC2 :
    sccregs = &m8260.scc2;
    break;
  case BSP_CPM_IRQ_SCC1 :
    sccregs = &m8260.scc1;
    break;
  default:
    break;
  }
  sccregs->sccm &= (~3);
}

int m8xx_scc_isOn(const rtems_irq_connect_data* ptr)
{
 return BSP_irq_enabled_at_cpm (ptr->name);
}

static rtems_irq_connect_data consoleIrqData =
{
  BSP_CPM_IRQ_SCC1,
  (rtems_irq_hdl)m8xx_scc1_interrupt_handler,
  (rtems_irq_enable) m8xx_scc_enable,
  (rtems_irq_disable) m8xx_scc_disable,
  (rtems_irq_is_enabled) m8xx_scc_isOn
};


void
m8xx_uart_scc_initialize (int minor)
{
  unsigned char brg;
  volatile m8260SCCparms_t *sccparms = 0;
  volatile m8260SCCRegisters_t *sccregs = 0;

  /*
   * Check that minor number is valid
   */
  if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) 
    return;

  /* Get the sicr clock source bit values for 9600 bps */
  brg = m8xx_get_brg(M8260_SCC_BRGS, 9600*16);

  m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) );
  m8260.cmxscr |= (brg<<(3+8*(3-(minor-SCC1_MINOR))));
  m8260.cmxscr |= (brg<<(8*(3-(minor-SCC1_MINOR))));

  /*
   * Allocate buffer descriptors
   */
  RxBd[minor] = m8xx_bd_allocate(1);
  TxBd[minor] = m8xx_bd_allocate(1);

  /*
   * Configure ports to enable TXDx and RXDx pins
   */

  m8260.ppard |=  (0x07 << ((minor-SCC1_MINOR)*3));
  m8260.psord &= ~(0x07 << ((minor-SCC1_MINOR)*3));
  if( minor == SCC1_MINOR )
    m8260.psord |= 0x02;
  m8260.pdird |=  (0x06 << ((minor-SCC1_MINOR)*3));
  m8260.pdird &= ~(0x01 << ((minor-SCC1_MINOR)*3));


  /*
   * Set up SMC1 parameter RAM common to all protocols
   */
  if( minor == SCC1_MINOR ) {
    sccparms = (m8260SCCparms_t*)&m8260.scc1p;
    sccregs  = (m8260SCCRegisters_t*)&m8260.scc1;
  }
  else if( minor == SCC2_MINOR ) {
    sccparms = (m8260SCCparms_t*)&m8260.scc2p;
    sccregs  = (m8260SCCRegisters_t*)&m8260.scc2;
  }
  else if( minor == SCC3_MINOR ) {
    sccparms = (m8260SCCparms_t*)&m8260.scc3p;
    sccregs  = (m8260SCCRegisters_t*)&m8260.scc3;
  }
  else {
    sccparms = (m8260SCCparms_t*)&m8260.scc4p;
    sccregs  = (m8260SCCRegisters_t*)&m8260.scc4;
  }
  
  sccparms->rbase = (char *)RxBd[minor] - (char *)&m8260;
  sccparms->tbase = (char *)TxBd[minor] - (char *)&m8260;




  sccparms->rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS;
  sccparms->tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS;
  if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 )
    sccparms->mrblr = RXBUFSIZE;    /* Maximum Rx buffer size */
  else
    sccparms->mrblr = 1;            /* Maximum Rx buffer size */
  sccparms->un.uart.max_idl = 10;   /* Set nb of idle chars to close buffer */
  sccparms->un.uart.brkcr = 0;      /* Set nb of breaks to send for STOP Tx */

  sccparms->un.uart.parec = 0;      /* Clear parity error counter */
  sccparms->un.uart.frmec = 0;      /* Clear framing error counter */
  sccparms->un.uart.nosec = 0;      /* Clear noise counter */
  sccparms->un.uart.brkec = 0;      /* Clear break counter */

  sccparms->un.uart.uaddr[0] = 0;   /* Not in multidrop mode, so clear */