mpc8260.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define M8260_CR_FCC2		 ((5<<26)|(17<<21))  /* FCC2 page and code */
#define M8260_CR_FCC2_ATM	 ((5<<26)|(14<<21))  /* FCC2 ATM mode page and code */
#define M8260_CR_FCC3		 ((6<<26)|(18<<21))  /* FCC3 page and code */
#define M8260_CR_SCC1		 ((0<<26)|(4<<21))   /* SCC1 page and code */
#define M8260_CR_SCC2		 ((1<<26)|(5<<21))   /* SCC2 page and code */
#define M8260_CR_SCC3		 ((2<<26)|(6<<21))   /* SCC3 page and code */
#define M8260_CR_SCC4		 ((3<<26)|(7<<21))   /* SCC4 page and code */
#define M8260_CR_SMC1		 ((7<<26)|(8<<21))   /* SMC1 page and code */
#define M8260_CR_SMC2		 ((8<<26)|(9<<21))   /* SMC2 page and code */
#define M8260_CR_RAND		 ((10<<26)|(14<<21)) /* SMC2 page and code */
#define M8260_CR_SPI		 ((9<<26)|(10<<21))  /* SPI page and code */
#define M8260_CR_I2C		 ((10<<26)|(11<<21)) /* I2C page and code */
#define M8260_CR_TMR		 ((10<<26)|(15<<21)) /* Timer page and code */
#define M8260_CR_MCC1		 ((7<<26)|(28<<21))  /* MCC1 page and code */
#define M8260_CR_MCC2		 ((8<<26)|(29<<21))  /* MCC2 page and code */
#define M8260_CR_IDMA1		 ((7<<26)|(20<<21))  /* IDMA1 page and code */
#define M8260_CR_IDMA2		 ((8<<26)|(21<<21))  /* IDMA2 page and code */
#define M8260_CR_IDMA3		 ((9<<26)|(22<<21))  /* IDMA3 page and code */
#define M8260_CR_IDMA4		 ((10<<26)|(23<<21)) /* IDMA4 page and code */

#define M8260_CR_FLG		 (1<<16)   /* Command sempahore flag */

#define M8260_CR_MCC_CHAN(x)	 ((x)<<6)  /* MCC channel number */
#define M8260_CR_FCC_HDLC	 (0<<6)	   /* FCC HDLC/Transparent protocol code */
#define M8260_CR_FCC_ATM	 (10<<6)   /* FCC ATM protocol code */
#define M8260_CR_FCC_ETH	 (12<<6)   /* FCC Ethernet protocol code */

#define M8260_CR_OP_INIT_RX_TX   (0)       /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */
#define M8260_CR_OP_INIT_RX      (1)       /* FCC, SCC, SMC UART, SPI, I2C, MCC */
#define M8260_CR_OP_INIT_TX      (2)       /* FCC, SCC, SMC UART, SPI, I2C, MCC */
#define M8260_CR_OP_INIT_HUNT    (3)       /* FCC, SCC, SMC UART */
#define M8260_CR_OP_STOP_TX      (4)       /* FCC, SCC, SMC UART, MCC */
#define M8260_CR_OP_GR_STOP_TX   (5)       /* FCC, SCC */
#define M8260_CR_OP_RESTART_TX   (6)       /* FCC, SCC, SMC UART */
#define M8260_CR_OP_CLOSE_RX_BD  (7)       /* FCC, SCC, SMC UART, SPI, I2C */
#define M8260_CR_OP_SET_GRP_ADDR (8)       /* FCC, SCC */
#define M8260_CR_OP_SET_TIMER    (8)       /* Timer */
#define M8260_CR_OP_GCI_TIMEOUT  (9)       /* SMC GCI */
#define M8260_CR_OP_START_IDMA   (9)       /* IDMA */
#define M8260_CR_OP_STOP_RX	 	 (9)	   /* MCC */
#define M8260_CR_OP_ATM_TX	 	 (10)	   /* FCC */
#define M8260_CR_OP_RESET_BCS    (10)      /* SCC */
#define M8260_CR_OP_GCI_ABORT    (10)      /* SMC GCI */
#define M8260_CR_OP_STOP_IDMA    (11)      /* IDMA */
#define M8260_CR_OP_RANDOM	 	 (12)      /* RAND */

/*
*************************************************************************
*                 System Protection Control Register (SYPCR)            *
*************************************************************************
*/
#define M8260_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
#define M8260_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
#define M8260_SYPCR_BME          (1<<7)      /* Bus monitor enable */
#define M8260_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
#define M8260_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
#define M8260_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
#define M8260_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */

/*
*************************************************************************
*                        Memory Control Registers                       *
*************************************************************************
*/
#define M8260_UPM_AMX_8col       (0<<20)   /* 8 column DRAM */
#define M8260_UPM_AMX_9col       (1<<20)   /* 9 column DRAM */
#define M8260_UPM_AMX_10col      (2<<20)   /* 10 column DRAM */
#define M8260_UPM_AMX_11col      (3<<20)   /* 11 column DRAM */
#define M8260_UPM_AMX_12col      (4<<20)   /* 12 column DRAM */
#define M8260_UPM_AMX_13col      (5<<20)   /* 13 column DRAM */
#define M8260_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
#define M8260_MSR_WPER           (1<<7)    /* Write protection error */
#define M8260_MPTPR_PTP(x)       ((x)<<8)  /* Periodic timer prescaler */
#define M8260_BR_BA(x)           ((x)&0xffff8000) /* Base address */
#define M8260_BR_AT(x)           ((x)<<12) /* Address type */
#define M8260_BR_PS8             (1<<10)   /* 8 bit port */
#define M8260_BR_PS16            (2<<10)   /* 16 bit port */
#define M8260_BR_PS32            (0<<10)   /* 32 bit port */
#define M8260_BR_PARE            (1<<9)    /* Parity checking enable */
#define M8260_BR_WP              (1<<8)    /* Write protect */
#define M8260_BR_MS_GPCM         (0<<6)    /* GPCM */
#define M8260_BR_MS_UPMA         (2<<6)    /* UPM A */
#define M8260_BR_MS_UPMB         (3<<6)    /* UPM B */
#define M8260_MEMC_BR_V          (1<<0)    /* Base/Option register are valid */

#define M8260_MEMC_OR_32K        0xffff8000      /* Address range */
#define M8260_MEMC_OR_64K        0xffff0000
#define M8260_MEMC_OR_128K       0xfffe0000
#define M8260_MEMC_OR_256K       0xfffc0000
#define M8260_MEMC_OR_512K       0xfff80000
#define M8260_MEMC_OR_1M         0xfff00000
#define M8260_MEMC_OR_2M         0xffe00000
#define M8260_MEMC_OR_4M         0xffc00000
#define M8260_MEMC_OR_8M         0xff800000
#define M8260_MEMC_OR_16M        0xff000000
#define M8260_MEMC_OR_32M        0xfe000000
#define M8260_MEMC_OR_64M        0xfc000000
#define M8260_MEMC_OR_128        0xf8000000
#define M8260_MEMC_OR_256M       0xf0000000
#define M8260_MEMC_OR_512M       0xe0000000
#define M8260_MEMC_OR_1G         0xc0000000
#define M8260_MEMC_OR_2G         0x80000000
#define M8260_MEMC_OR_4G         0x00000000
#define M8260_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
#define M8260_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
#define M8260_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
#define M8260_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
#define M8260_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
#define M8260_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
#define M8260_MEMC_OR_BI         (1<8)       /* Burst inhibit */
#define M8260_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
#define M8260_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
#define M8260_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
#define M8260_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */

/*
*************************************************************************
*                         UPM Registers (MxMR)                          *
*************************************************************************
*/
#define M8260_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
#define M8260_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
#define M8260_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
#define M8260_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
#define M8260_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
#define M8260_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
#define M8260_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
#define M8260_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
/*
*************************************************************************
*                         Memory Command Register (MCR)                 *
*************************************************************************
*/
#define M8260_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
#define M8260_MEMC_MCR_READ      (1<<30)     /* READ command */
#define M8260_MEMC_MCR_RUN       (2<<30)     /* RUN command */
#define M8260_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
#define M8260_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
#define M8260_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
#define M8260_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
#define M8260_MEMC_MCR_MAD(x)    (x)         /* Machine address */



/*
*************************************************************************
*                         SI Mode Register (SIMODE)                     *
*************************************************************************
*/
#define M8260_SI_SMC2_BITS       0xFFFF0000	/* All SMC2 bits */
#define M8260_SI_SMC2_TDM        (1<<31) 	/* Multiplexed SMC2 */
#define M8260_SI_SMC2_BRG1       (0<<28) 	/* SMC2 clock souce */
#define M8260_SI_SMC2_BRG2       (1<<28)
#define M8260_SI_SMC2_BRG3       (2<<28)
#define M8260_SI_SMC2_BRG4       (3<<28)
#define M8260_SI_SMC2_CLK5       (0<<28)
#define M8260_SI_SMC2_CLK6       (1<<28)
#define M8260_SI_SMC2_CLK7       (2<<28)
#define M8260_SI_SMC2_CLK8       (3<<28)
#define M8260_SI_SMC1_BITS       0x0000FFFF	/* All SMC1 bits */
#define M8260_SI_SMC1_TDM        (1<<15) 	/* Multiplexed SMC1 */
#define M8260_SI_SMC1_BRG1       (0<<12) 	/* SMC1 clock souce */
#define M8260_SI_SMC1_BRG2       (1<<12)
#define M8260_SI_SMC1_BRG3       (2<<12)
#define M8260_SI_SMC1_BRG4       (3<<12)
#define M8260_SI_SMC1_CLK1       (0<<12)
#define M8260_SI_SMC1_CLK2       (1<<12)
#define M8260_SI_SMC1_CLK3       (2<<12)
#define M8260_SI_SMC1_CLK4       (3<<12)

/*
*************************************************************************
*                  SDMA Configuration Register (SDCR)                   *
*************************************************************************
*/
#define M8260_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
#define M8260_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */

/*
*************************************************************************
*                  SDMA Status Register (SDSR)                          *
*************************************************************************
*/
#define M8260_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
#define M8260_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
#define M8260_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */

/*
*************************************************************************
*                      Baud (sic) Rate Generators                       *
*************************************************************************
*/
#define M8260_BRG_RST            (1<<17)         /* Reset generator */
#define M8260_BRG_EN             (1<<16)         /* Enable generator */
#define M8260_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
#define M8260_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
#define M8260_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
#define M8260_BRG_ATB            (1<<13)         /* Autobaud */
#define M8260_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
#define M8260_BRG_57600          (32<<1)
#define M8260_BRG_38400          (64<<1)
#define M8260_BRG_19200          (129<<1)
#define M8260_BRG_9600           (259<<1)
#define M8260_BRG_4800           (520<<1)
#define M8260_BRG_2400           (1040<<1)
#define M8260_BRG_1200           (2082<<1)
#define M8260_BRG_600            ((259<<1) | 1)
#define M8260_BRG_300            ((520<<1) | 1)
#define M8260_BRG_150            ((1040<<1) | 1)
#define M8260_BRG_75             ((2080<<1) | 1)

#define M8xx_BRG_RST             (1<<17)         /* Reset generator */
#define M8xx_BRG_EN              (1<<16)         /* Enable generator */
#define M8xx_BRG_EXTC_BRGCLK     (0<<14)         /* Source is BRGCLK */

#define M8260_BRG1		(1<<7)
#define M8260_BRG2		(1<<6)
#define M8260_BRG3		(1<<5)
#define M8260_BRG4		(1<<4)
#define M8260_BRG5		(1<<3)
#define M8260_BRG6		(1<<2)
#define M8260_BRG7		(1<<1)
#define M8260_BRG8		(1<<0)



#define M8260_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
#define M8260_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
#define M8260_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
#define M8260_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
#define M8260_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
#define M8260_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
#define M8260_TGCR_STP1          (1<<1)    /* Stop timer */
#define M8260_TGCR_STP2          (1<<5)    /* Stop timer */
#define M8260_TGCR_STP3          (1<<9)    /* Stop timer */
#define M8260_TGCR_STP4          (1<<13)   /* Stop timer */
#define M8260_TGCR_RST1          (1<<0)    /* Enable timer */
#define M8260_TGCR_RST2          (1<<4)    /* Enable timer */
#define M8260_TGCR_RST3          (1<<8)    /* Enable timer */
#define M8260_TGCR_RST4          (1<<12)   /* Enable timer */
#define M8260_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
#define M8260_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */

#define M8260_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
#define M8260_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
#define M8260_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
#define M8260_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
#define M8260_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
#define M8260_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
#define M8260_TMR_RESTART        (1<<3)    /* Restart timer after reference */
#define M8260_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
#define M8260_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
#define M8260_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
#define M8260_TMR_TGATE          (1<<0)    /* TGATE controls timer */

#ifdef REV_0_2
#define M8260_PISCR_PS           (1<<6)    /* PIT Interrupt state */
#else
#define M8260_PISCR_PS           (1<<7)    /* PIT Interrupt state */
#endif
#define M8260_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
#define M8260_PISCR_PTF          (1<<1)    /* Stop timer when freeze asserted */
#define M8260_PISCR_PTE          (1<<0)    /* PIT enable */

#if 0
#define M8260_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
#define M8260_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
#define M8260_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
#define M8260_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
#define M8260_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
#define M8260_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
#define M8260_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
#endif

#define M8260_TMCNTSC_SEC	 (1<<7)	   /* per second flag */
#define M8260_TMCNTSC_ALR	 (1<<6)	   /* Alarm interrupt flag */
#define M8260_TMCNTSC_SIE	 (1<<3)	   /* per second interrupt enable */
#define M8260_TMCNTSC_ALE	 (1<<2)	   /* Alarm interrupt enable */
#define M8260_TMCNTSC_TCF	 (1<<1)	   /* Time count frequency */
#define M8260_TMCNTSC_TCE	 (1<<0)	   /* Time count enable */

#define M8260_SIMASK_PC0		 (1<<31)
#define M8260_SIMASK_PC1		 (1<<30)
#define M8260_SIMASK_PC2		 (1<<29)
#define M8260_SIMASK_PC3		 (1<<28)
#define M8260_SIMASK_PC4		 (1<<27)
#define M8260_SIMASK_PC5		 (1<<26)
#define M8260_SIMASK_PC6		 (1<<25)
#define M8260_SIMASK_PC7		 (1<<24)
#define M8260_SIMASK_PC8		 (1<<23)
#define M8260_SIMASK_PC9		 (1<<22)
#define M8260_SIMASK_PC10		 (1<<21)
#define M8260_SIMASK_PC11		 (1<<20)
#define M8260_SIMASK_PC12		 (1<<19)
#define M8260_SIMASK_PC13		 (1<<18)
#define M8260_SIMASK_PC14		 (1<<17)
#define M8260_SIMASK_PC15		 (1<<16)
#define M8260_SIMASK_IRQ1		 (1<<14)
#define M8260_SIMASK_IRQ2		 (1<<13)
#define M8260_SIMASK_IRQ3		 (1<<12)
#define M8260_SIMASK_IRQ4		 (1<<11)
#define M8260_SIMASK_IRQ5		 (1<<10)
#define M8260_SIMASK_IRQ6		 (1<<9)
#define M8260_SIMASK_IRQ7		 (1<<8)
#define M8260_SIMASK_TMCNT		 (1<<2)
#define M8260_SIMASK_PIT		 (1<<1)

#define M8260_SIMASK_FCC1		 (1<<31)
#define M8260_SIMASK_FCC2		 (1<<30)
#define M8260_SIMASK_FCC3		 (1<<29)
#define M8260_SIMASK_MCC1		 (1<<27)
#define M8260_SIMASK_MCC2		 (1<<26)
#define M8260_SIMASK_SCC1		 (1<<23)
#define M8260_SIMASK_SCC2		 (1<<22)
#define M8260_SIMASK_SCC3		 (1<<21)
#define M8260_SIMASK_SCC4		 (1<<20)
#define M8260_SIMASK_I2C		 (1<<15)
#define M8260_SIMASK_SPI		 (1<<14)
#define M8260_SIMASK_RTT		 (1<<13)
#define M8260_SIMASK_SMC1		 (1<<12)
#define M8260_SIMASK_SMC2		 (1<<11)
#define M8260_SIMASK_IDMA1		 (1<<10)
#define M8260_SIMASK_IDMA2		 (1<<9)
#define M8260_SIMASK_IDMA3		 (1<<8)
#define M8260_SIMASK_IDMA4		 (1<<7)
#define M8260_SIMASK_SDMA		 (1<<6)
#define M8260_SIMASK_TIMER1		 (1<<4)
#define M8260_SIMASK_TIMER2		 (1<<3)
#define M8260_SIMASK_TIMER3		 (1<<2)
#define M8260_SIMASK_TIMER4		 (1<<1)

#define M8260_SIUMCR_EARB        (1<<31)
#define M8260_SIUMCR_EARP0       (0<<28)
#define M8260_SIUMCR_EARP1       (1<<28)
#define M8260_SIUMCR_EARP2       (2<<28)
#define M8260_SIUMCR_EARP3       (3<<28)
#define M8260_SIUMCR_EARP4       (4<<28)
#define M8260_SIUMCR_EARP5       (5<<28)
#define M8260_SIUMCR_EARP6       (6<<28)
#define M8260_SIUMCR_EARP7       (7<<28)
#define M8260_SIUMCR_DSHW        (1<<23)
#define M8260_SIUMCR_DBGC0       (0<<21)
#define M8260_SIUMCR_DBGC1       (1<<21)
#define M8260_SIUMCR_DBGC2       (2<<21)
#define M8260_SIUMCR_DBGC3       (3<<21)
#define M8260_SIUMCR_DBPC0       (0<<19)
#define M8260_SIUMCR_DBPC1       (1<<19)
#define M8260_SIUMCR_DBPC2       (2<<19)
#define M8260_SIUMCR_DBPC3       (3<<19)
#define M8260_SIUMCR_FRC         (1<<17)
#define M8260_SIUMCR_DLK         (1<<16)
#define M8260_SIUMCR_PNCS        (1<<15)
#define M8260_SIUMCR_OPAR        (1<<14)
#define M8260_SIUMCR_DPC         (1<<13)
#define M8260_SIUMCR_MPRE        (1<<12)
#define M8260_SIUMCR_MLRC0       (0<<10)
#define M8260_SIUMCR_MLRC1       (1<<10)
#define M8260_SIUMCR_MLRC2       (2<<10)
#define M8260_SIUMCR_MLRC3       (3<<10)
#define M8260_SIUMCR_AEME        (1<<9)
#define M8260_SIUMCR_SEME        (1<<8)
#define M8260_SIUMCR_BSC         (1<<7)
#define M8260_SIUMCR_GB5E        (1<<6)
#define M8260_SIUMCR_B2DD        (1<<5)
#define M8260_SIUMCR_B3DD        (1<<4)

/*
*************************************************************************
*                 MPC8260 DUAL-PORT RAM AND REGISTERS                   *
*************************************************************************
*/
typedef struct m8260_ {

  /*
   * CPM Dual-Port RAM
   */
  rtems_unsigned8   dpram1[16384];		/* 0x0000 - 0x3FFF BD/data/ucode */
  rtems_unsigned8	cpm_pad0[16384];	/* 0x4000 - 0x7FFF Reserved      */