mpc8260.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define M8260_SCCE_TX    (1<<1)
#define M8260_SCCE_RX    (1<<0)


/*
*************************************************************************
*                   Fast Serial Communication Controllers               *
*************************************************************************
*/


typedef struct m8260FCCparms_ {
  rtems_unsigned16        riptr;
  rtems_unsigned16        tiptr;
  rtems_unsigned16        _pad0;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        rstate;
  rtems_unsigned32        rbase;
  rtems_unsigned16        _rbdstat;
  rtems_unsigned16        _rbdlen;
  rtems_unsigned32        _rdptr;
  rtems_unsigned32        tstate;
  rtems_unsigned32        tbase;
  rtems_unsigned16        _tbdstat;
  rtems_unsigned16        _tbdlen;
  rtems_unsigned32        _tdptr;
  rtems_unsigned32        _rbptr;
  rtems_unsigned32        _tbptr;
  rtems_unsigned32        _rcrc;
  rtems_unsigned32        _pad1;
  rtems_unsigned32        _tcrc;

  union {
    struct {
      rtems_unsigned32	      _pad0;
      rtems_unsigned32	      _pad1;
      rtems_unsigned32	      c_mask;
      rtems_unsigned32	      c_pres;
      rtems_unsigned16	      disfc;
      rtems_unsigned16	      crcec;
      rtems_unsigned16	      abtsc;
      rtems_unsigned16	      nmarc;
      rtems_unsigned32	      _max_cnt;
      rtems_unsigned16	      mflr;
      rtems_unsigned16	      rfthr;
      rtems_unsigned16	      rfcnt;
      rtems_unsigned16	      hmask;
      rtems_unsigned16	      haddr1;
      rtems_unsigned16	      haddr2;
      rtems_unsigned16	      haddr3;
      rtems_unsigned16	      haddr4;
      rtems_unsigned16	      _ts_tmp;
      rtems_unsigned16	      _tmp_mb;
    } hdlc;
    struct {
      rtems_unsigned32	      _pad0;
      rtems_unsigned32	      _pad1;
      rtems_unsigned32	      c_mask;
      rtems_unsigned32	      c_pres;
      rtems_unsigned16	      disfc;
      rtems_unsigned16	      crcec;
      rtems_unsigned16	      abtsc;
      rtems_unsigned16	      nmarc;
      rtems_unsigned32	      _max_cnt;
      rtems_unsigned16	      mflr;
      rtems_unsigned16	      rfthr;
      rtems_unsigned16	      rfcnt;
      rtems_unsigned16	      hmask;
      rtems_unsigned16	      haddr1;
      rtems_unsigned16	      haddr2;
      rtems_unsigned16	      haddr3;
      rtems_unsigned16	      haddr4;
      rtems_unsigned16	      _ts_tmp;
      rtems_unsigned16	      _tmp_mb;
    } transparent;
    struct {
      rtems_unsigned32        _stat_buf;
      rtems_unsigned32        cam_ptr;
      rtems_unsigned32        c_mask;
      rtems_unsigned32        c_pres;
      rtems_unsigned32        crcec;
      rtems_unsigned32        alec;
      rtems_unsigned32        disfc;
      rtems_unsigned16        ret_lim;
      rtems_unsigned16        _ret_cnt;
      rtems_unsigned16        p_per;
      rtems_unsigned16        _boff_cnt;
      rtems_unsigned32        gaddr_h;
      rtems_unsigned32        gaddr_l;
      rtems_unsigned16        tfcstat;
      rtems_unsigned16        tfclen;
      rtems_unsigned32        tfcptr;
      rtems_unsigned16        mflr;
      rtems_unsigned16        paddr1_h;
      rtems_unsigned16        paddr1_m;
      rtems_unsigned16        paddr1_l;
      rtems_unsigned16        _ibd_cnt;
      rtems_unsigned16        _ibd_start;
      rtems_unsigned16        _ibd_end;
      rtems_unsigned16        _tx_len;
      rtems_unsigned16        _ibd_base;
      rtems_unsigned32        iaddr_h;
      rtems_unsigned32        iaddr_l;
      rtems_unsigned16        minflr;
      rtems_unsigned16        taddr_h;
      rtems_unsigned16        taddr_m;
      rtems_unsigned16        taddr_l;
      rtems_unsigned16        pad_ptr;
      rtems_unsigned16        _pad0;
      rtems_unsigned16        _cf_range;
      rtems_unsigned16        _max_b;
      rtems_unsigned16        maxd1;
      rtems_unsigned16        maxd2;
      rtems_unsigned16        _maxd;
      rtems_unsigned16        _dma_cnt;
      rtems_unsigned32        octc;
      rtems_unsigned32        colc;
      rtems_unsigned32        broc;
      rtems_unsigned32        mulc;
      rtems_unsigned32        uspc;
      rtems_unsigned32        frgc;
      rtems_unsigned32        ospc;
      rtems_unsigned32        jbrc;
      rtems_unsigned32        p64c;
      rtems_unsigned32        p65c;
      rtems_unsigned32        p128c;
      rtems_unsigned32        p256c;
      rtems_unsigned32        p512c;
      rtems_unsigned32        p1024c;
      rtems_unsigned32        _cam_buf;
      rtems_unsigned32        _pad1;
    } ethernet;
  } un;
} m8260FCCparms_t;


/*
 * Receive and transmit function code register bits
 * These apply to the function code registers of all devices, not just SCC.
 */
#define M8260_RFCR_BO(x)         ((x)<<3)
#define M8260_RFCR_MOT           (2<<3)
#define M8260_RFCR_LOCAL_BUS	 (2)
#define M8260_RFCR_60X_BUS	 (0)
#define M8260_TFCR_BO(x)         ((x)<<3)
#define M8260_TFCR_MOT           (2<<3)
#define M8260_TFCR_LOCAL_BUS	 (2)
#define M8260_TFCR_60X_BUS	 (0)

/*
*************************************************************************
*                     Serial Management Controllers                     *
*************************************************************************
*/
typedef struct m8260SMCparms_ {
  rtems_unsigned16        rbase;
  rtems_unsigned16        tbase;
  rtems_unsigned8         rfcr;
  rtems_unsigned8         tfcr;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        _rstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _rbptr;
  rtems_unsigned16        _pad1;
  rtems_unsigned32        _pad2;
  rtems_unsigned32        _tstate;
  rtems_unsigned32        _pad3;
  rtems_unsigned16        _tbptr;
  rtems_unsigned16        _pad4;
  rtems_unsigned32        _pad5;
  union {
    struct {
      rtems_unsigned16	  max_idl;
      rtems_unsigned16	  _idlc;
      rtems_unsigned16	  _brkln;
      rtems_unsigned16	  brkec;
      rtems_unsigned16	  brkcr;
      rtems_unsigned16	  _r_mask;
    } uart;
    struct {
      rtems_unsigned16	  _pad0[6];
    } transparent;
  } un;
  rtems_unsigned32	  _pad6;
} m8260SMCparms_t;

/*
 * Mode register
 */
#define M8260_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
#define M8260_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
#define M8260_SMCMR_PARITY               (1<<9)       /* Enable parity */
#define M8260_SMCMR_EVEN                 (1<<8)       /* Even parity */
#define M8260_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
#define M8260_SMCMR_SM_UART              (2<<4)       /* UART Mode */
#define M8260_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
#define M8260_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
#define M8260_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
#define M8260_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
#define M8260_SMCMR_REN                  (1<<0)       /* Enable receiver */

/*
 * Event and mask registers (SMCE, SMCM)
 */
#define M8260_SMCE_TXE   (1<<4)
#define M8260_SMCE_BSY   (1<<2)
#define M8260_SMCE_TX    (1<<1)
#define M8260_SMCE_RX    (1<<0)

/*
*************************************************************************
*                      Serial Peripheral Interface                      *
*************************************************************************
*/
typedef struct m8260SPIparms_ {
  rtems_unsigned16        rbase;
  rtems_unsigned16        tbase;
  rtems_unsigned8         rfcr;
  rtems_unsigned8         tfcr;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        _rstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _rbptr;
  rtems_unsigned16        _pad1;
  rtems_unsigned32        _pad2;
  rtems_unsigned32        _tstate;
  rtems_unsigned32        _pad3;
  rtems_unsigned16        _tbptr;
  rtems_unsigned16        _pad4;
  rtems_unsigned32        _pad5;
} m8260SPIparms_t;

/*
 * Mode register (SPMODE)
 */
#define M8260_SPMODE_LOOP                (1<<14)  /* Local loopback mode */
#define M8260_SPMODE_CI                  (1<<13)  /* Clock invert */
#define M8260_SPMODE_CP                  (1<<12)  /* Clock phase */
#define M8260_SPMODE_DIV16               (1<<11)  /* Divide BRGCLK by 16 */
#define M8260_SPMODE_REV                 (1<<10)  /* Reverse data */
#define M8260_SPMODE_MASTER              (1<<9)   /* SPI is master */
#define M8260_SPMODE_EN                  (1<<8)   /* Enable SPI */
#define M8260_SPMODE_CLEN(x)             ((x)<<4) /* Character length */
#define M8260_SPMODE_PM(x)               (x)      /* Prescaler modulus */

/*
 * Mode register (SPCOM)
 */
#define M8260_SPCOM_STR                  (1<<7)  /* Start transmit */

/*
 * Event and mask registers (SPIE, SPIM)
 */
#define M8260_SPIE_MME   (1<<5)          /* Multi-master error */
#define M8260_SPIE_TXE   (1<<4)          /* Tx error */
#define M8260_SPIE_BSY   (1<<2)          /* Busy condition*/
#define M8260_SPIE_TXB   (1<<1)          /* Tx buffer */
#define M8260_SPIE_RXB   (1<<0)          /* Rx buffer */

/*
*************************************************************************
*                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
*************************************************************************
*/
typedef struct m8260BufferDescriptor_ {
  rtems_unsigned16        status;
  rtems_unsigned16        length;
  volatile void           *buffer;
} m8260BufferDescriptor_t;

/*
 * Bits in receive buffer descriptor status word
 */
#define M8260_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8260_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8260_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8260_BD_LAST            (1<<11) /* Ethernet, SPI */
#define M8260_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
#define M8260_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
#define M8260_BD_ADDRESS         (1<<10) /* SCC UART */
#define M8260_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
#define M8260_BD_MISS            (1<<8)  /* Ethernet */
#define M8260_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
#define M8260_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
#define M8260_BD_LONG            (1<<5)  /* Ethernet, SCC HDLC */
#define M8260_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
#define M8260_BD_NONALIGNED      (1<<4)  /* Ethernet, SCC HDLC */
#define M8260_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
#define M8260_BD_SHORT           (1<<3)  /* Ethernet */
#define M8260_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
#define M8260_BD_ABORT		 (1<<3)  /* SCC HDLC */
#define M8260_BD_CRC_ERROR       (1<<2)  /* Ethernet, SCC HDLC */
#define M8260_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
#define M8260_BD_COLLISION       (1<<0)  /* Ethernet */
#define M8260_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
#define M8260_BD_MASTER_ERROR    (1<<0)  /* SPI */

#define M8xx_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_LAST            (1<<11) /* Ethernet, SPI */
#define M8xx_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
#define M8xx_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
#define M8xx_BD_ADDRESS         (1<<10) /* SCC UART */
#define M8xx_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
#define M8xx_BD_MISS            (1<<8)  /* Ethernet */
#define M8xx_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
#define M8xx_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
#define M8xx_BD_LONG            (1<<5)  /* Ethernet, SCC HDLC */
#define M8xx_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
#define M8xx_BD_NONALIGNED      (1<<4)  /* Ethernet, SCC HDLC */
#define M8xx_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
#define M8xx_BD_SHORT           (1<<3)  /* Ethernet */
#define M8xx_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
#define M8xx_BD_ABORT		 (1<<3)  /* SCC HDLC */
#define M8xx_BD_CRC_ERROR       (1<<2)  /* Ethernet, SCC HDLC */
#define M8xx_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_COLLISION       (1<<0)  /* Ethernet */
#define M8xx_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
#define M8xx_BD_MASTER_ERROR    (1<<0)  /* SPI */

/*
 * Bits in transmit buffer descriptor status word
 * Many bits have the same meaning as those in receiver buffer descriptors.
 */
#define M8260_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8260_BD_PAD             (1<<14) /* Ethernet */
#define M8260_BD_CTS_REPORT      (1<<11) /* SCC UART */
#define M8260_BD_TX_CRC          (1<<10) /* Ethernet */
#define M8260_BD_DEFER           (1<<9)  /* Ethernet */
#define M8260_BD_HEARTBEAT       (1<<8)  /* Ethernet */
#define M8260_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
#define M8260_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
#define M8260_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
#define M8260_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
#define M8260_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
#define M8260_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI, SCC HDLC */
#define M8260_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
#define M8260_BD_CTS_LOST        (1<<0)  /* SCC UART, SCC HDLC */

#define M8xx_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_PAD             (1<<14) /* Ethernet */
#define M8xx_BD_CTS_REPORT      (1<<11) /* SCC UART */
#define M8xx_BD_TX_CRC          (1<<10) /* Ethernet */
#define M8xx_BD_DEFER           (1<<9)  /* Ethernet */
#define M8xx_BD_HEARTBEAT       (1<<8)  /* Ethernet */
#define M8xx_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
#define M8xx_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
#define M8xx_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
#define M8xx_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
#define M8xx_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
#define M8xx_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI, SCC HDLC */
#define M8xx_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
#define M8xx_BD_CTS_LOST        (1<<0)  /* SCC UART, SCC HDLC */

/*
*************************************************************************
*                           IDMA Buffer Descriptors                     *
*************************************************************************
*/
typedef struct m8260IDMABufferDescriptor_ {
  rtems_unsigned16        status;
  rtems_unsigned8         dfcr;       
  rtems_unsigned8         sfcr;       
  rtems_unsigned32        length;
  void                    *source;
  void                    *destination;
} m8260IDMABufferDescriptor_t;

/*
*************************************************************************
*       RISC Communication Processor Module Command Register (CR)       *
*************************************************************************
*/
#define M8260_CR_RST             (1<<31)   	     /* Reset communication processor */

#define M8260_CR_FCC1		 ((4<<26)|(16<<21))  /* FCC1 page and code */
#define M8260_CR_FCC1_ATM	 ((4<<26)|(14<<21))  /* FCC1 ATM mode page and code */