mpc8260.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/* buggy version of CPU */
#define REV_0_2

/*
**************************************************************************
**************************************************************************
**                                                                      **
**  MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER    **
**                             POWERQUICC II                            **
**                                                                      **
**                        HARDWARE DECLARATIONS                         **
**                                                                      **
**                                                                      **
**  Submitted by:							**
**      Andy Dachs							**							**
**	Surrey Satellite Technology Limited				**					**
**	http://www.sstl.co.uk						**						**
**	[e-mail]						**								**
**                                                                      **
**  Based on previous submissions for other PPC variants by:	        **
**								        **
**  Submitted By:                                                       **
**                                                                      **
**      W. Eric Norum                                                   **
**      Saskatchewan Accelerator Laboratory                             **
**      University of Saskatchewan                                      **
**      107 North Road                                                  **
**      Saskatoon, Saskatchewan, CANADA                                 **
**      S7N 5C6                                                         **
**                                                                      **
**      [e-mail]                                           **
**                                                                      **
**  Modified for use with the MPC860 (original code was for MC68360)    **
**  by                                                                  **
**      Jay Monkman                                                     **
**      Frasca International, Inc.                                      **
**      906 E. Airport Rd.                                              **
**      Urbana, IL, 61801                                               **
**                                                                      **
**      [e-mail]                                             **
**																		**
**                                                                      **
**************************************************************************
**************************************************************************
*/

#ifndef __MPC8260_h
#define __MPC8260_h

#ifndef ASM
/*
  Macros for SPRs
*/




/*
*************************************************************************
*                         REGISTER SUBBLOCKS                            *
*************************************************************************
*/


/*
 * Memory controller registers
 */
typedef struct m8260MEMCRegisters_ {
  rtems_unsigned32        br;
  rtems_unsigned32        _or;  /* or is a C++ keyword :( */
} m8260MEMCRegisters_t;


/*
 * Fast Communication Controller Registers
*/
typedef struct m8260FCCRegisters_ {
  rtems_unsigned32    gfmr;
  rtems_unsigned32	  fpsmr;
  rtems_unsigned16	  ftodr;
  rtems_unsigned8	  fcc_pad0[2];
  rtems_unsigned16	  fdsr;
  rtems_unsigned8	  fcc_pad1[2];
  rtems_unsigned32	  fcce;
  rtems_unsigned32	  fccm;
  rtems_unsigned8	  fccs;
  rtems_unsigned8	  fcc_pad2[3];
  rtems_unsigned8	  ftirr_phy0;			/* n/a on FCC3 */
  rtems_unsigned8	  ftirr_phy1;           /* n/a on FCC3 */
  rtems_unsigned8	  ftirr_phy2;			/* n/a on FCC3 */
  rtems_unsigned8	  ftirr_phy3;			/* n/a on FCC3 */
} m8260FCCRegisters_t;


/*
 * Serial Communications Controller registers
 */
typedef struct m8260SCCRegisters_ {
  rtems_unsigned32        gsmr_l;
  rtems_unsigned32        gsmr_h;
  rtems_unsigned16        psmr;
  rtems_unsigned8         scc_pad0[2];
  rtems_unsigned16        todr;
  rtems_unsigned16        dsr;
  rtems_unsigned16        scce;
  rtems_unsigned8	  scc_pad2[2];
  rtems_unsigned16        sccm;
  rtems_unsigned8	  scc_pad3[1];
  rtems_unsigned8         sccs;
  rtems_unsigned8         scc_pad1[8];
} m8260SCCRegisters_t;

/*
 * Serial Management Controller registers
 */
typedef struct m8260SMCRegisters_ {
  rtems_unsigned8         smc_pad0[2];
  rtems_unsigned16        smcmr;
  rtems_unsigned8	  smc_pad2[2];
  rtems_unsigned8         smce;
  rtems_unsigned8	  smc_pad3[3];
  rtems_unsigned8         smcm;
  rtems_unsigned8         smc_pad1[5];
} m8260SMCRegisters_t;


/*
 * Serial Interface With Time Slot Assigner Registers
 */
typedef struct m8260SIRegisters_ {
  rtems_unsigned16	  siamr;
  rtems_unsigned16	  sibmr;
  rtems_unsigned16	  sicmr;
  rtems_unsigned16	  sidmr;
  rtems_unsigned8	  sigmr;
  rtems_unsigned8	  si_pad0[1];
  rtems_unsigned8	  sicmdr;
  rtems_unsigned8	  si_pad1[1];
  rtems_unsigned8	  sistr;
  rtems_unsigned8	  si_pad2[1];
  rtems_unsigned16	  sirsr;
} m8260SIRegisters_t;


/*
 * Multi Channel Controller registers
 */
typedef struct m8260MCCRegisters_ {
  rtems_unsigned16	  mcce;
  rtems_unsigned8	  mcc_pad2[2];
  rtems_unsigned16	  mccm;
  rtems_unsigned16	  mcc_pad0;
  rtems_unsigned8	  mccf;
  rtems_unsigned8	  mcc_pad1[7];
} m8260MCCRegisters_t;


/*
*************************************************************************
*                              RISC Timers                              *
*************************************************************************
*/
/*
typedef struct m8260TimerParms_ {
  rtems_unsigned16        tm_base;
  rtems_unsigned16        _tm_ptr;
  rtems_unsigned16        _r_tmr;
  rtems_unsigned16        _r_tmv;
  rtems_unsigned32        tm_cmd;
  rtems_unsigned32        tm_cnt;
} m8260TimerParms_t;
*/

/*
 * RISC Controller Configuration Register (RCCR)
 * All other bits in this register are reserved.
 */
#define M8260_RCCR_TIME          (1<<31)    /* Enable timer */
#define M8260_RCCR_TIMEP(x)      ((x)<<24)  /* Timer period */
#define M8260_RCCR_DR1M          (1<<23)    /* IDMA Rqst 1 Mode */
#define M8260_RCCR_DR2M          (1<<22)    /* IDMA Rqst 2 Mode */
#define M8260_RCCR_DR1QP(x)      ((x)<<20)  /* IDMA1 Rqst Priority */
#define M8260_RCCR_EIE           (1<<19)    /* External Interrupt Enable */
#define M8260_RCCR_SCD           (1<<18)    /* Scheduler Configuration */
#define M8260_RCCR_DR2QP(x)      ((x)<<16)  /* IDMA2 Rqst Priority */
#define M8260_RCCR_ERAM(x)       ((x)<<13)  /* Enable RAM Microcode */
#define M8260_RCCR_EDM1          (1<<11)    /* DRQ1 Edge detect mode */
#define M8260_RCCR_EDM2          (1<<10)    /* DRQ2 Edge detect mode */
#define M8260_RCCR_EDM3          (1<<9)     /* DRQ3 Edge detect mode */
#define M8260_RCCR_EDM4          (1<<8)     /* DRQ4 Edge detect mode */
#define M8260_RCCR_DR3M          (1<<7)     /* IDMA Rqst 1 Mode */
#define M8260_RCCR_DR4M          (1<<6)     /* IDMA Rqst 2 Mode */
#define M8260_RCCR_DR3QP(x)      ((x)<<4)   /* IDMA3 Rqst Priority */
#define M8260_RCCR_DEM12         (1<<3)     /* DONE1,2 Edge detect mode */
#define M8260_RCCR_DEM34         (1<<2)     /* DONE3,4 Edge detect mode */
#define M8260_RCCR_DR4QP(x)      (x)   	    /* IDMA4 Rqst Priority */



/*
 * Command register
 * Set up this register before issuing a M8260_CR_OP_SET_TIMER command.
 */
#if 0
#define M8260_TM_CMD_V           (1<<31)         /* Set to enable timer */
#define M8260_TM_CMD_R           (1<<30)         /* Set for automatic restart */
#define M8260_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
#define M8260_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
#define M8260_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */
#endif

/*
*************************************************************************
*                               DMA Controllers                         *
*************************************************************************
*/
typedef struct m8260IDMAparms_ {
  rtems_unsigned16        ibase;
  rtems_unsigned16        dcm;
  rtems_unsigned16		  ibdptr;
  rtems_unsigned16		  dpr_buf;
  rtems_unsigned16		  _buf_inv;
  rtems_unsigned16		  ssmax;
  rtems_unsigned16		  _dpr_in_ptr;
  rtems_unsigned16		  sts;
  rtems_unsigned16		  _dpr_out_ptr;
  rtems_unsigned16		  seob;
  rtems_unsigned16		  deob;
  rtems_unsigned16		  dts;
  rtems_unsigned16		  _ret_add;
  rtems_unsigned16		  reserved;
  rtems_unsigned32		  _bd_cnt;
  rtems_unsigned32		  _s_ptr;
  rtems_unsigned32		  _d_ptr;
  rtems_unsigned32		  istate;
} m8260IDMAparms_t;


/*
*************************************************************************
*                   Serial Communication Controllers                    *
*************************************************************************
*/


typedef struct m8260SCCparms_ {
  rtems_unsigned16        rbase;
  rtems_unsigned16        tbase;
  rtems_unsigned8         rfcr;
  rtems_unsigned8         tfcr;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        _rstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _rbptr;
  rtems_unsigned16        _pad1;
  rtems_unsigned32        _pad2;
  rtems_unsigned32        _tstate;
  rtems_unsigned32        _pad3;
  rtems_unsigned16        _tbptr;
  rtems_unsigned16        _pad4;
  rtems_unsigned32        _pad5;
  rtems_unsigned32        _rcrc;
  rtems_unsigned32        _tcrc;
  union {
    struct {
      rtems_unsigned32        _res0;
      rtems_unsigned32        _res1;
      rtems_unsigned16        max_idl;
      rtems_unsigned16        idlc;
      rtems_unsigned16        brkcr;
      rtems_unsigned16        parec;
      rtems_unsigned16        frmec;
      rtems_unsigned16        nosec;
      rtems_unsigned16        brkec;
      rtems_unsigned16        brklen;
      rtems_unsigned16        uaddr[2];
      rtems_unsigned16        rtemp;
      rtems_unsigned16        toseq;
      rtems_unsigned16        character[8];
      rtems_unsigned16        rccm;
      rtems_unsigned16        rccr;
      rtems_unsigned16        rlbc;
    } uart;
    struct {
      rtems_unsigned32	      _pad0;
      rtems_unsigned32	      c_mask;
      rtems_unsigned32	      c_pres;
      rtems_unsigned16	      disfc;
      rtems_unsigned16	      crcec;
      rtems_unsigned16	      abtsc;
      rtems_unsigned16	      nmarc;
      rtems_unsigned16	      retrc;
      rtems_unsigned16	      mflr;
      rtems_unsigned16	      _max_cnt;
      rtems_unsigned16	      rfthr;
      rtems_unsigned16	      _rfcnt;
      rtems_unsigned16	      hmask;
      rtems_unsigned16	      haddr1;
      rtems_unsigned16	      haddr2;
      rtems_unsigned16	      haddr3;
      rtems_unsigned16	      haddr4;
      rtems_unsigned16	      _tmp;
      rtems_unsigned16	      _tmp_mb;
    } hdlc;
    struct {
      rtems_unsigned32        _pad0;
      rtems_unsigned32        crcc;
      rtems_unsigned16        prcrc;
      rtems_unsigned16        ptcrc;
      rtems_unsigned16        parec;
      rtems_unsigned16        bsync;
      rtems_unsigned16        bdle;
      rtems_unsigned16        character[8];
      rtems_unsigned16        rccm;
    } bisync;
    struct {
      rtems_unsigned32	      _crc_p;
      rtems_unsigned32	      _crc_c;
    } transparent;
    struct {
      rtems_unsigned32        c_pres;
      rtems_unsigned32        c_mask;
      rtems_unsigned32        crcec;
      rtems_unsigned32        alec;
      rtems_unsigned32        disfc;
      rtems_unsigned16        pads;
      rtems_unsigned16        ret_lim;
      rtems_unsigned16        _ret_cnt;
      rtems_unsigned16        mflr;
      rtems_unsigned16        minflr;
      rtems_unsigned16        maxd1;
      rtems_unsigned16        maxd2;
      rtems_unsigned16        _maxd;
      rtems_unsigned16        _dma_cnt;
      rtems_unsigned16        _max_b;
      rtems_unsigned16        gaddr1;
      rtems_unsigned16        gaddr2;
      rtems_unsigned16        gaddr3;
      rtems_unsigned16        gaddr4;
      rtems_unsigned32        _tbuf0data0;
      rtems_unsigned32        _tbuf0data1;
      rtems_unsigned32        _tbuf0rba0;
      rtems_unsigned32        _tbuf0crc;
      rtems_unsigned16        _tbuf0bcnt;
      rtems_unsigned16        paddr_h;
      rtems_unsigned16        paddr_m;
      rtems_unsigned16        paddr_l;
      rtems_unsigned16        p_per;
      rtems_unsigned16        _rfbd_ptr;
      rtems_unsigned16        _tfbd_ptr;
      rtems_unsigned16        _tlbd_ptr;
      rtems_unsigned32        _tbuf1data0;
      rtems_unsigned32        _tbuf1data1;
      rtems_unsigned32        _tbuf1rba0;
      rtems_unsigned32        _tbuf1crc;
      rtems_unsigned16        _tbuf1bcnt;
      rtems_unsigned16        _tx_len;
      rtems_unsigned16        iaddr1;
      rtems_unsigned16        iaddr2;
      rtems_unsigned16        iaddr3;
      rtems_unsigned16        iaddr4;
      rtems_unsigned16        _boff_cnt;
      rtems_unsigned16        taddr_l;
      rtems_unsigned16        taddr_m;
      rtems_unsigned16        taddr_h;
    } ethernet;
  } un;
} m8260SCCparms_t;


/*
 * Event and mask registers (SCCE, SCCM)
 */
#define M8260_SCCE_BRKE  (1<<6)
#define M8260_SCCE_BRK   (1<<5)
#define M8260_SCCE_TXE   (1<<4)
#define M8260_SCCE_RXF   (1<<3)
#define M8260_SCCE_BSY   (1<<2)