console-generic.c

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

  switch (minor) {
    case SMC1_MINOR:
    case SMC2_MINOR:
      return m8xx_smc_set_attributes( minor, t );

    case SCC2_MINOR:
    case SCC3_MINOR:
    case SCC4_MINOR:
      return m8xx_scc_set_attributes( minor, t );
  }
  return 0;
}


/*
 * Interrupt handlers
 */
static void m8xx_scc2_interrupt_handler ()
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if ((m8xx.scc2.sccm & M8xx_SCCE_RX) && (m8xx.scc2.scce & M8xx_SCCE_RX)) {
    m8xx.scc2.scce = M8xx_SCCE_RX;    /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SCC2_MINOR]->buffer, 
        RxBd[SCC2_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SCC2_MINOR],
        (char *)RxBd[SCC2_MINOR]->buffer,
        (int)RxBd[SCC2_MINOR]->length );
      RxBd[SCC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
                                 M8xx_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8xx.scc2.scce & M8xx_SCCE_TX) {
    m8xx.scc2.scce = M8xx_SCCE_TX;  /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SCC2_MINOR]->status & M8xx_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SCC2_MINOR],
        (int)TxBd[SCC2_MINOR]->length);
  }
}


#ifdef mpc860
static void
m8xx_scc3_interrupt_handler (void)
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if ((m8xx.scc3.sccm & M8xx_SCCE_RX) && (m8xx.scc3.scce & M8xx_SCCE_RX)) {
    m8xx.scc3.scce = M8xx_SCCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SCC3_MINOR]->buffer, 
        RxBd[SCC3_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SCC3_MINOR],
        (char *)RxBd[SCC3_MINOR]->buffer,
        (int)RxBd[SCC3_MINOR]->length );
      RxBd[SCC3_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
                                 M8xx_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8xx.scc3.scce & M8xx_SCCE_TX) {
    m8xx.scc3.scce = M8xx_SCCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SCC3_MINOR]->status & M8xx_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SCC3_MINOR],
        (int)TxBd[SCC3_MINOR]->length);
  }
}


static void
m8xx_scc4_interrupt_handler (void)
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if ((m8xx.scc4.sccm & M8xx_SCCE_RX) && (m8xx.scc4.scce & M8xx_SCCE_RX)) {
    m8xx.scc4.scce = M8xx_SCCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SCC4_MINOR]->buffer, 
        RxBd[SCC4_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SCC4_MINOR],
        (char *)RxBd[SCC4_MINOR]->buffer,
        (int)RxBd[SCC4_MINOR]->length );
      RxBd[SCC4_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
                                 M8xx_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8xx.scc4.scce & M8xx_SCCE_TX) {
    m8xx.scc4.scce = M8xx_SCCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SCC4_MINOR]->status & M8xx_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SCC4_MINOR],
        (int)TxBd[SCC4_MINOR]->length);
  }
}
#endif

static void
m8xx_smc1_interrupt_handler (void)
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if (m8xx.smc1.smce & M8xx_SMCE_RX) {
    m8xx.smc1.smce = M8xx_SMCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SMC1_MINOR]->buffer, 
        RxBd[SMC1_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SMC1_MINOR],
        (char *)RxBd[SMC1_MINOR]->buffer,
        (int)RxBd[SMC1_MINOR]->length );
      RxBd[SMC1_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
                                 M8xx_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8xx.smc1.smce & M8xx_SMCE_TX) {
    m8xx.smc1.smce = M8xx_SMCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SMC1_MINOR]->status & M8xx_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SMC1_MINOR],
        (int)TxBd[SMC1_MINOR]->length);
  }
}


static void
m8xx_smc2_interrupt_handler (void)
{
  int nb_overflow;

  /*
   * Buffer received?
   */
  if (m8xx.smc2.smce & M8xx_SMCE_RX) {
    m8xx.smc2.smce = M8xx_SMCE_RX;  /* Clear the event */


    /* Check that the buffer is ours */
    if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
      rtems_cache_invalidate_multiple_data_lines( 
        (const void *) RxBd[SMC2_MINOR]->buffer, 
        RxBd[SMC2_MINOR]->length );
      nb_overflow = rtems_termios_enqueue_raw_characters(
        (void *)ttyp[SMC2_MINOR],
        (char *)RxBd[SMC2_MINOR]->buffer,
        (int)RxBd[SMC2_MINOR]->length );
      RxBd[SMC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
                                 M8xx_BD_INTERRUPT;
    }
  }

  /*
   * Buffer transmitted?
   */
  if (m8xx.smc2.smce & M8xx_SMCE_TX) {
    m8xx.smc2.smce = M8xx_SMCE_TX;    /* Clear the event */

    /* Check that the buffer is ours */
    if ((TxBd[SMC2_MINOR]->status & M8xx_BD_READY) == 0)
      rtems_termios_dequeue_characters (
        (void *)ttyp[SMC2_MINOR],
        (int)TxBd[SMC2_MINOR]->length);
  }
}

void m8xx_scc_enable(const rtems_irq_connect_data* ptr)
{
  volatile m8xxSCCRegisters_t *sccregs = 0;
  switch (ptr->name) {
#if defined(mpc860)
  case BSP_CPM_IRQ_SCC4 :
    sccregs = &m8xx.scc4;
    break;
  case BSP_CPM_IRQ_SCC3 :
    sccregs = &m8xx.scc3;
    break;
#endif
  case BSP_CPM_IRQ_SCC2 :
    sccregs = &m8xx.scc2;
    break;
  case BSP_CPM_IRQ_SCC1 :
    sccregs = &m8xx.scc1;
    break;
  default:
    break;
  }
  sccregs->sccm = 3;
}

void m8xx_scc_disable(const rtems_irq_connect_data* ptr)
{
  volatile m8xxSCCRegisters_t *sccregs = 0;
  switch (ptr->name) {
#if defined(mpc860)
  case BSP_CPM_IRQ_SCC4 :
    sccregs = &m8xx.scc4;
    break;
  case BSP_CPM_IRQ_SCC3 :
    sccregs = &m8xx.scc3;
    break;
#endif
  case BSP_CPM_IRQ_SCC2 :
    sccregs = &m8xx.scc2;
    break;
  case BSP_CPM_IRQ_SCC1 :
    sccregs = &m8xx.scc1;
    break;
  default:
    break;
  }
  sccregs->sccm &= (~3);
}

int m8xx_scc_isOn(const rtems_irq_connect_data* ptr)
{
 return BSP_irq_enabled_at_cpm (ptr->name);
}

static rtems_irq_connect_data consoleIrqData;
	
void
m8xx_uart_scc_initialize (int minor)
{
  unsigned char brg;
  volatile m8xxSCCparms_t *sccparms = 0;
  volatile m8xxSCCRegisters_t *sccregs = 0;

  /*
   * Check that minor number is valid
   */
  if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) 
    return;

  /* Get the sicr clock source bit values for 9600 bps */
  brg = m8xx_get_brg_clk(9600);

  /*
   * Allocate buffer descriptors
   */
  RxBd[minor] = m8xx_bd_allocate(1);
  TxBd[minor] = m8xx_bd_allocate(1);

  /*
   *  Get the address of the parameter RAM for the specified port,
   *  configure I/O port A,C & D and put SMC in NMSI mode, connect
   *  the SCC to the appropriate BRG.
   *
   *  SCC2 TxD is shared with port A bit 12
   *  SCC2 RxD is shared with port A bit 13
   *  SCC1 TxD is shared with port A bit 14
   *  SCC1 RxD is shared with port A bit 15
   *  SCC4 DCD is shared with port C bit 4
   *  SCC4 CTS is shared with port C bit 5
   *  SCC3 DCD is shared with port C bit 6
   *  SCC3 CTS is shared with port C bit 7
   *  SCC2 DCD is shared with port C bit 8
   *  SCC2 CTS is shared with port C bit 9
   *  SCC1 DCD is shared with port C bit 10
   *  SCC1 CTS is shared with port C bit 11
   *  SCC2 RTS is shared with port C bit 14
   *  SCC1 RTS is shared with port C bit 15
   *  SCC4 RTS is shared with port D bit 6
   *  SCC3 RTS is shared with port D bit 7
   *  SCC4 TxD is shared with port D bit 8
   *  SCC4 RxD is shared with port D bit 9
   *  SCC3 TxD is shared with port D bit 10
   *  SCC3 RxD is shared with port D bit 11
   */
  switch (minor) {
    case SCC2_MINOR:
      sccparms = &m8xx.scc2p;
      sccregs = &m8xx.scc2;
      
      m8xx.papar |=  0x000C;        /* PA12 & PA13 are dedicated peripheral pins */
      m8xx.padir &= ~0x000C;        /* PA13 & PA12 must not drive the UART lines */
      m8xx.paodr &= ~0x000C;        /* PA12 & PA13 are not open drain */
      m8xx.pcpar |=  0x0002;        /* PC14 is SCC2 RTS */
      m8xx.pcpar &= ~0x00C0;        /* PC8 & PC9 are SCC2 DCD and CTS */
      m8xx.pcdir &= ~0x00C2;        /* PC8, PC9 & PC14 must not drive the UART lines */
      m8xx.pcso  |=  0x00C0;        /* Enable DCD and CTS inputs */
      
      m8xx.sicr &= 0xFFFF00FF;      /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */
      m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */
      break;

#ifdef mpc860
    case SCC3_MINOR:
      sccparms = &m8xx.scc3p;
      sccregs = &m8xx.scc3;
      
      m8xx.pcpar &= ~0x0300;        /* PC6 & PC7 are SCC3 DCD and CTS */
      m8xx.pcdir &= ~0x0300;        /* PC6 & PC7 must not drive the UART lines */
      m8xx.pcso  |=  0x0300;        /* Enable DCD and CTS inputs */
      m8xx.pdpar |=  0x0130;        /* PD7, PD10 & PD11 are dedicated peripheral pins */
      
      m8xx.sicr &= 0xFF00FFFF;      /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */
      m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */
      break;

    case SCC4_MINOR:
      sccparms = &m8xx.scc4p;
      sccregs = &m8xx.scc4;
      
      m8xx.pcpar &= ~0x0C00;        /* PC4 & PC5 are SCC4 DCD and CTS */
      m8xx.pcdir &= ~0x0C00;        /* PC4 & PC5 must not drive the UART lines */
      m8xx.pcso  |=  0x0C00;        /* Enable DCD and CTS inputs */
      m8xx.pdpar |=  0x02C0;        /* PD6, PD8 & PD9 are dedicated peripheral pins */
       
      m8xx.sicr &= 0x00FFFFFF;      /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */
      m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */