mpc8xx.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define M8xx_CR_CHAN_SCC2       (4<<4)
#define M8xx_CR_CHAN_SPI        (5<<4)
#define M8xx_CR_CHAN_IDMA2      (5<<4)
#define M8xx_CR_CHAN_TIMER      (5<<4)
#define M8xx_CR_CHAN_SCC3       (8<<4)
#define M8xx_CR_CHAN_SMC1       (9<<4)
#define M8xx_CR_CHAN_DSP1       (9<<4)
#define M8xx_CR_CHAN_SCC4       (12<<4)
#define M8xx_CR_CHAN_SMC2       (13<<4)
#define M8xx_CR_CHAN_DSP2       (13<<4)
#define M8xx_CR_FLG             (1<<0)  /* Command flag */

/*
*************************************************************************
*                 System Protection Control Register (SYPCR)            *
*************************************************************************
*/
#define M8xx_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
#define M8xx_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
#define M8xx_SYPCR_BME          (1<<7)      /* Bus monitor enable */
#define M8xx_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
#define M8xx_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
#define M8xx_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
#define M8xx_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */

/*
*************************************************************************
*                 PCMCIA Control Registers
*************************************************************************
*/
#define M8xx_PCMCIA_POR_BSIZE_1B    (0x00 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_2B    (0x01 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_4B    (0x03 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_8B    (0x02 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_16B   (0x06 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_32B   (0x07 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_64B   (0x05 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_128B  (0x04 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_256B  (0x0C << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_512B  (0x0D << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_1KB   (0x0F << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_2KB   (0x0E << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_4KB   (0x0A << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_8KB   (0x0B << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_16KB  (0x09 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_32KB  (0x08 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_64KB  (0x18 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_1MB   (0x1E << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_2MB   (0x1F << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_4MB   (0x1D << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_8MB   (0x1C << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_16MB  (0x14 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_32MB  (0x15 << (31-4))
#define M8xx_PCMCIA_POR_BSIZE_64MB  (0x17 << (31-4))

#define M8xx_PCMCIA_POR_PSHT(x)     (((x) & 0x0f) << (31-15))
#define M8xx_PCMCIA_POR_PSST(x)     (((x) & 0x0f) << (31-19))
#define M8xx_PCMCIA_POR_PSL(x)      (((x) & 0x1f) << (31-24))
#define M8xx_PCMCIA_POR_PPS_8       ((0) << (31-19))
#define M8xx_PCMCIA_POR_PPS_16      ((1) << (31-19))

#define M8xx_PCMCIA_POR_PRS_MEM     ((0) << (31-28))
#define M8xx_PCMCIA_POR_PRS_ATT     ((2) << (31-28))
#define M8xx_PCMCIA_POR_PRS_IO      ((3) << (31-28))
#define M8xx_PCMCIA_POR_PRS_DMA     ((4) << (31-28))
#define M8xx_PCMCIA_POR_PRS_DML     ((5) << (31-28))

#define M8xx_PCMCIA_POR_PSLOT_A     ((0) << (31-29))
#define M8xx_PCMCIA_POR_PSLOT_B     ((1) << (31-29))

#define M8xx_PCMCIA_POR_WP          ((1) << (31-30))
#define M8xx_PCMCIA_POR_VALID       ((1) << (31-31))

#define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7))
#define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15))
#define M8xx_PCMCIA_PGCR_CDRQ_OFF    ((0) << (31-17))
#define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17))
#define M8xx_PCMCIA_PGCR_CDRQ_SPKR   ((3) << (31-17))
#define M8xx_PCMCIA_PGCR_COE         ((1) << (31-24))
#define M8xx_PCMCIA_PGCR_CRESET      ((1) << (31-25))

#define M8xx_PCMCIA_PIPR_CAVS1      ((1) << (31- 0))
#define M8xx_PCMCIA_PIPR_CAVS2      ((1) << (31- 1))
#define M8xx_PCMCIA_PIPR_CAWP       ((1) << (31- 2))
#define M8xx_PCMCIA_PIPR_CACD2      ((1) << (31- 3))
#define M8xx_PCMCIA_PIPR_CACD1      ((1) << (31- 4))
#define M8xx_PCMCIA_PIPR_CABVD2     ((1) << (31- 5))
#define M8xx_PCMCIA_PIPR_CABVD1     ((1) << (31- 6))
#define M8xx_PCMCIA_PIPR_CARDY      ((1) << (31- 7))
#define M8xx_PCMCIA_PIPR_CBVS1      ((1) << (31-16))
#define M8xx_PCMCIA_PIPR_CBVS2      ((1) << (31-17))
#define M8xx_PCMCIA_PIPR_CBWP       ((1) << (31-18))
#define M8xx_PCMCIA_PIPR_CBCD2      ((1) << (31-19))
#define M8xx_PCMCIA_PIPR_CBCD1      ((1) << (31-20))
#define M8xx_PCMCIA_PIPR_CBBVD2     ((1) << (31-21))
#define M8xx_PCMCIA_PIPR_CBBVD1     ((1) << (31-22))
#define M8xx_PCMCIA_PIPR_CBRDY      ((1) << (31-23))


#define M8xx_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
#define M8xx_SYPCR_BME          (1<<7)      /* Bus monitor enable */
#define M8xx_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
#define M8xx_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
#define M8xx_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
#define M8xx_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */

/*
*************************************************************************
*                        Memory Control Registers                       *
*************************************************************************
*/
#define M8xx_UPM_AMX_8col       (0<<20) /* 8 column DRAM */
#define M8xx_UPM_AMX_9col       (1<<20) /* 9 column DRAM */
#define M8xx_UPM_AMX_10col      (2<<20) /* 10 column DRAM */
#define M8xx_UPM_AMX_11col      (3<<20) /* 11 column DRAM */
#define M8xx_UPM_AMX_12col      (4<<20) /* 12 column DRAM */
#define M8xx_UPM_AMX_13col      (5<<20) /* 13 column DRAM */
#define M8xx_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
#define M8xx_MSR_WPER           (1<<7)  /* Write protection error */
#define M8xx_MPTPR_PTP(x)       ((x)<<8) /* Periodic timer prescaler */
#define M8xx_BR_BA(x)           ((x)&0xffff8000) /* Base address */
#define M8xx_BR_AT(x)           ((x)<<12) /* Address type */
#define M8xx_BR_PS8             (1<<10)  /* 8 bit port */
#define M8xx_BR_PS16            (2<<10)  /* 16 bit port */
#define M8xx_BR_PS32            (0<<10)  /* 32 bit port */
#define M8xx_BR_PARE            (1<<9)   /* Parity checking enable */
#define M8xx_BR_WP              (1<<8)   /* Write protect */
#define M8xx_BR_MS_GPCM         (0<<6)   /* GPCM */
#define M8xx_BR_MS_UPMA         (2<<6)   /* UPM A */
#define M8xx_BR_MS_UPMB         (3<<6)   /* UPM B */
#define M8xx_MEMC_BR_V          (1<<0)  /* Base/Option register are valid */

#define M8xx_MEMC_OR_32K        0xffff8000      /* Address range */
#define M8xx_MEMC_OR_64K        0xffff0000
#define M8xx_MEMC_OR_128K       0xfffe0000
#define M8xx_MEMC_OR_256K       0xfffc0000
#define M8xx_MEMC_OR_512K       0xfff80000
#define M8xx_MEMC_OR_1M         0xfff00000
#define M8xx_MEMC_OR_2M         0xffe00000
#define M8xx_MEMC_OR_4M         0xffc00000
#define M8xx_MEMC_OR_8M         0xff800000
#define M8xx_MEMC_OR_16M        0xff000000
#define M8xx_MEMC_OR_32M        0xfe000000
#define M8xx_MEMC_OR_64M        0xfc000000
#define M8xx_MEMC_OR_128        0xf8000000
#define M8xx_MEMC_OR_256M       0xf0000000
#define M8xx_MEMC_OR_512M       0xe0000000
#define M8xx_MEMC_OR_1G         0xc0000000
#define M8xx_MEMC_OR_2G         0x80000000
#define M8xx_MEMC_OR_4G         0x00000000
#define M8xx_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
#define M8xx_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
#define M8xx_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
#define M8xx_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
#define M8xx_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
#define M8xx_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
#define M8xx_MEMC_OR_BI         (1<<8)      /* Burst inhibit */
#define M8xx_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
#define M8xx_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
#define M8xx_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
#define M8xx_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */

/*
*************************************************************************
*                         UPM Registers (MxMR)                          *
*************************************************************************
*/
#define M8xx_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
#define M8xx_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
#define M8xx_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
#define M8xx_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
#define M8xx_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
#define M8xx_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
#define M8xx_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
#define M8xx_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
/*
*************************************************************************
*                         Memory Command Register (MCR)                 *
*************************************************************************
*/
#define M8xx_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
#define M8xx_MEMC_MCR_READ      (1<<30)     /* READ command */
#define M8xx_MEMC_MCR_RUN       (2<<30)     /* RUN command */
#define M8xx_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
#define M8xx_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
#define M8xx_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
#define M8xx_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
#define M8xx_MEMC_MCR_MAD(x)    (x)         /* Machine address */



/*
*************************************************************************
*                         SI Mode Register (SIMODE)                     *
*************************************************************************
*/
#define M8xx_SI_SMC2_BITS       0xFFFF0000      /* All SMC2 bits */
#define M8xx_SI_SMC2_TDM        (1<<31) /* Multiplexed SMC2 */
#define M8xx_SI_SMC2_BRG1       (0<<28) /* SMC2 clock souce */
#define M8xx_SI_SMC2_BRG2       (1<<28)
#define M8xx_SI_SMC2_BRG3       (2<<28)
#define M8xx_SI_SMC2_BRG4       (3<<28)
#define M8xx_SI_SMC2_CLK5       (0<<28)
#define M8xx_SI_SMC2_CLK6       (1<<28)
#define M8xx_SI_SMC2_CLK7       (2<<28)
#define M8xx_SI_SMC2_CLK8       (3<<28)
#define M8xx_SI_SMC1_BITS       0x0000FFFF      /* All SMC1 bits */
#define M8xx_SI_SMC1_TDM        (1<<15) /* Multiplexed SMC1 */
#define M8xx_SI_SMC1_BRG1       (0<<12) /* SMC1 clock souce */
#define M8xx_SI_SMC1_BRG2       (1<<12)
#define M8xx_SI_SMC1_BRG3       (2<<12)
#define M8xx_SI_SMC1_BRG4       (3<<12)
#define M8xx_SI_SMC1_CLK1       (0<<12)
#define M8xx_SI_SMC1_CLK2       (1<<12)
#define M8xx_SI_SMC1_CLK3       (2<<12)
#define M8xx_SI_SMC1_CLK4       (3<<12)

/*
*************************************************************************
*                  SDMA Configuration Register (SDCR)                   *
*************************************************************************
*/
#define M8xx_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
#define M8xx_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */

/*
*************************************************************************
*                  SDMA Status Register (SDSR)                          *
*************************************************************************
*/
#define M8xx_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
#define M8xx_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
#define M8xx_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */

/*
*************************************************************************
*                      Baud (sic) Rate Generators                       *
*************************************************************************
*/
#define M8xx_BRG_RST            (1<<17)         /* Reset generator */
#define M8xx_BRG_EN             (1<<16)         /* Enable generator */
#define M8xx_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
#define M8xx_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
#define M8xx_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
#define M8xx_BRG_ATB            (1<<13)         /* Autobaud */
#define M8xx_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
#define M8xx_BRG_57600          (32<<1)
#define M8xx_BRG_38400          (64<<1)
#define M8xx_BRG_19200          (129<<1)
#define M8xx_BRG_9600           (259<<1)
#define M8xx_BRG_4800           (520<<1)
#define M8xx_BRG_2400           (1040<<1)
#define M8xx_BRG_1200           (2082<<1)
#define M8xx_BRG_600            ((259<<1) | 1)
#define M8xx_BRG_300            ((520<<1) | 1)
#define M8xx_BRG_150            ((1040<<1) | 1)
#define M8xx_BRG_75             ((2080<<1) | 1)

#define M8xx_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
#define M8xx_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
#define M8xx_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
#define M8xx_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
#define M8xx_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
#define M8xx_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
#define M8xx_TGCR_STP1          (1<<1)    /* Stop timer */
#define M8xx_TGCR_STP2          (1<<5)    /* Stop timer */
#define M8xx_TGCR_STP3          (1<<9)    /* Stop timer */
#define M8xx_TGCR_STP4          (1<<13)   /* Stop timer */
#define M8xx_TGCR_RST1          (1<<0)    /* Enable timer */
#define M8xx_TGCR_RST2          (1<<4)    /* Enable timer */
#define M8xx_TGCR_RST3          (1<<8)    /* Enable timer */
#define M8xx_TGCR_RST4          (1<<12)   /* Enable timer */
#define M8xx_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
#define M8xx_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */

#define M8xx_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
#define M8xx_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
#define M8xx_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
#define M8xx_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
#define M8xx_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
#define M8xx_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
#define M8xx_TMR_RESTART        (1<<3)    /* Restart timer after reference */
#define M8xx_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
#define M8xx_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
#define M8xx_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
#define M8xx_TMR_TGATE          (1<<0)    /* TGATE controls timer */

#define M8xx_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
#define M8xx_PISCR_PS           (1<<7)    /* PIT Interrupt state */
#define M8xx_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
#define M8xx_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
#define M8xx_PISCR_PTE          (1<<0)    /* PIT enable */

#define M8xx_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
#define M8xx_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
#define M8xx_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
#define M8xx_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
#define M8xx_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
#define M8xx_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
#define M8xx_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */

#define M8xx_SIMASK_IRM0        (1<<31)
#define M8xx_SIMASK_LVM0        (1<<30)
#define M8xx_SIMASK_IRM1        (1<<29)
#define M8xx_SIMASK_LVM1        (1<<28)
#define M8xx_SIMASK_IRM2        (1<<27)
#define M8xx_SIMASK_LVM2        (1<<26)
#define M8xx_SIMASK_IRM3        (1<<25)
#define M8xx_SIMASK_LVM3        (1<<24)
#define M8xx_SIMASK_IRM4        (1<<23)
#define M8xx_SIMASK_LVM4        (1<<22)
#define M8xx_SIMASK_IRM5        (1<<21)
#define M8xx_SIMASK_LVM5        (1<<20)
#define M8xx_SIMASK_IRM6        (1<<19)
#define M8xx_SIMASK_LVM6        (1<<18)
#define M8xx_SIMASK_IRM7        (1<<17)
#define M8xx_SIMASK_LVM7        (1<<16)

#define M8xx_SIUMCR_EARB        (1<<31)
#define M8xx_SIUMCR_EARP0       (0<<28)
#define M8xx_SIUMCR_EARP1       (1<<28)
#define M8xx_SIUMCR_EARP2       (2<<28)
#define M8xx_SIUMCR_EARP3       (3<<28)
#define M8xx_SIUMCR_EARP4       (4<<28)
#define M8xx_SIUMCR_EARP5       (5<<28)
#define M8xx_SIUMCR_EARP6       (6<<28)
#define M8xx_SIUMCR_EARP7       (7<<28)
#define M8xx_SIUMCR_DSHW        (1<<23)
#define M8xx_SIUMCR_DBGC0       (0<<21)
#define M8xx_SIUMCR_DBGC1       (1<<21)
#define M8xx_SIUMCR_DBGC2       (2<<21)
#define M8xx_SIUMCR_DBGC3       (3<<21)
#define M8xx_SIUMCR_DBPC0       (0<<19)
#define M8xx_SIUMCR_DBPC1       (1<<19)
#define M8xx_SIUMCR_DBPC2       (2<<19)
#define M8xx_SIUMCR_DBPC3       (3<<19)
#define M8xx_SIUMCR_FRC         (1<<17)
#define M8xx_SIUMCR_DLK         (1<<16)
#define M8xx_SIUMCR_PNCS        (1<<15)
#define M8xx_SIUMCR_OPAR        (1<<14)
#define M8xx_SIUMCR_DPC         (1<<13)
#define M8xx_SIUMCR_MPRE        (1<<12)
#define M8xx_SIUMCR_MLRC0       (0<<10)
#define M8xx_SIUMCR_MLRC1       (1<<10)
#define M8xx_SIUMCR_MLRC2       (2<<10)
#define M8xx_SIUMCR_MLRC3       (3<<10)
#define M8xx_SIUMCR_AEME        (1<<9)
#define M8xx_SIUMCR_SEME        (1<<8)
#define M8xx_SIUMCR_BSC         (1<<7)
#define M8xx_SIUMCR_GB5E        (1<<6)
#define M8xx_SIUMCR_B2DD        (1<<5)
#define M8xx_SIUMCR_B3DD        (1<<4)

/*
 *  Value to write to a key register to unlock the corresponding SIU register
 */
#define M8xx_UNLOCK_KEY         0x55CCAA33
 
/*
*************************************************************************
*   MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address)   *
*************************************************************************
*/
typedef struct m8xx_ {
        
  /*
   * SIU Block
   */