mpc8xx.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

  rtems_unsigned16        _pad2;
  rtems_unsigned16        _yptr;
  rtems_unsigned16        _m;
  rtems_unsigned16        _pad3;
  rtems_unsigned16        _n;
  rtems_unsigned16        _pad4;
  rtems_unsigned16        _k;
  rtems_unsigned16        _pad5;
} m8xxDSPparms_t;

/*
*************************************************************************
*                   Serial Communication Controllers                    *
*************************************************************************
*/
typedef struct m8xxSCCparms_ {
  rtems_unsigned16        rbase;
  rtems_unsigned16        tbase;
  rtems_unsigned8         rfcr;
  rtems_unsigned8         tfcr;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        _rstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _rbptr;
  rtems_unsigned16        _pad1;
  rtems_unsigned32        _pad2;
  rtems_unsigned32        _tstate;
  rtems_unsigned32        _pad3;
  rtems_unsigned16        _tbptr;
  rtems_unsigned16        _pad4;
  rtems_unsigned32        _pad5;
  rtems_unsigned32        _rcrc;
  rtems_unsigned32        _tcrc;
  union {
    struct {
      rtems_unsigned32        _res0;
      rtems_unsigned32        _res1;
      rtems_unsigned16        max_idl;
      rtems_unsigned16        _idlc;
      rtems_unsigned16        brkcr;
      rtems_unsigned16        parec;
      rtems_unsigned16        frmec;
      rtems_unsigned16        nosec;
      rtems_unsigned16        brkec;
      rtems_unsigned16        brkln;
      rtems_unsigned16        uaddr[2];
      rtems_unsigned16        _rtemp;
      rtems_unsigned16        toseq;
      rtems_unsigned16        character[8];
      rtems_unsigned16        rccm;
      rtems_unsigned16        rccr;
      rtems_unsigned16        rlbc;
    } uart;
  } un;
} m8xxSCCparms_t;

typedef struct m8xxSCCENparms_ {
  rtems_unsigned16        rbase;
  rtems_unsigned16        tbase;
  rtems_unsigned8         rfcr;
  rtems_unsigned8         tfcr;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        _rstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _rbptr;
  rtems_unsigned16        _pad1;
  rtems_unsigned32        _pad2;
  rtems_unsigned32        _tstate;
  rtems_unsigned32        _pad3;
  rtems_unsigned16        _tbptr;
  rtems_unsigned16        _pad4;
  rtems_unsigned32        _pad5;
  rtems_unsigned32        _rcrc;
  rtems_unsigned32        _tcrc;
  union {
    struct {
      rtems_unsigned32        _res0;
      rtems_unsigned32        _res1;
      rtems_unsigned16        max_idl;
      rtems_unsigned16        _idlc;
      rtems_unsigned16        brkcr;
      rtems_unsigned16        parec;
      rtems_unsigned16        frmec;
      rtems_unsigned16        nosec;
      rtems_unsigned16        brkec;
      rtems_unsigned16        brkln;
      rtems_unsigned16        uaddr[2];
      rtems_unsigned16        _rtemp;
      rtems_unsigned16        toseq;
      rtems_unsigned16        character[8];
      rtems_unsigned16        rccm;
      rtems_unsigned16        rccr;
      rtems_unsigned16        rlbc;
    } uart;
    struct {
      rtems_unsigned32        c_pres;
      rtems_unsigned32        c_mask;
      rtems_unsigned32        crcec;
      rtems_unsigned32        alec;
      rtems_unsigned32        disfc;
      rtems_unsigned16        pads;
      rtems_unsigned16        ret_lim;
      rtems_unsigned16        _ret_cnt;
      rtems_unsigned16        mflr;
      rtems_unsigned16        minflr;
      rtems_unsigned16        maxd1;
      rtems_unsigned16        maxd2;
      rtems_unsigned16        _maxd;
      rtems_unsigned16        dma_cnt;
      rtems_unsigned16        _max_b;
      rtems_unsigned16        gaddr1;
      rtems_unsigned16        gaddr2;
      rtems_unsigned16        gaddr3;
      rtems_unsigned16        gaddr4;
      rtems_unsigned32        _tbuf0data0;
      rtems_unsigned32        _tbuf0data1;
      rtems_unsigned32        _tbuf0rba0;
      rtems_unsigned32        _tbuf0crc;
      rtems_unsigned16        _tbuf0bcnt;
      rtems_unsigned16        paddr_h;
      rtems_unsigned16        paddr_m;
      rtems_unsigned16        paddr_l;
      rtems_unsigned16        p_per;
      rtems_unsigned16        _rfbd_ptr;
      rtems_unsigned16        _tfbd_ptr;
      rtems_unsigned16        _tlbd_ptr;
      rtems_unsigned32        _tbuf1data0;
      rtems_unsigned32        _tbuf1data1;
      rtems_unsigned32        _tbuf1rba0;
      rtems_unsigned32        _tbuf1crc;
      rtems_unsigned16        _tbuf1bcnt;
      rtems_unsigned16        _tx_len;
      rtems_unsigned16        iaddr1;
      rtems_unsigned16        iaddr2;
      rtems_unsigned16        iaddr3;
      rtems_unsigned16        iaddr4;
      rtems_unsigned16        _boff_cnt;
      rtems_unsigned16        taddr_h;
      rtems_unsigned16        taddr_m;
      rtems_unsigned16        taddr_l;
    } ethernet;
  } un;
} m8xxSCCENparms_t;

/*
 * Receive and transmit function code register bits
 * These apply to the function code registers of all devices, not just SCC.
 */
#define M8xx_RFCR_BO(x)         ((x)<<3)
#define M8xx_RFCR_MOT           (2<<3)
#define M8xx_RFCR_DMA_SPACE(x)  (x)
#define M8xx_TFCR_BO(x)         ((x)<<3)
#define M8xx_TFCR_MOT           (2<<3)
#define M8xx_TFCR_DMA_SPACE(x)  (x)

/*
 * Event and mask registers (SCCE, SCCM)
 */
#define M8xx_SCCE_BRKE  (1<<6)
#define M8xx_SCCE_BRK   (1<<4)
#define M8xx_SCCE_BSY   (1<<2)
#define M8xx_SCCE_TX    (1<<1)
#define M8xx_SCCE_RX    (1<<0)

/*
*************************************************************************
*                     Serial Management Controllers                     *
*************************************************************************
*/
typedef struct m8xxSMCparms_ {
  rtems_unsigned16        rbase;
  rtems_unsigned16        tbase;
  rtems_unsigned8         rfcr;
  rtems_unsigned8         tfcr;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        _rstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _rbptr;
  rtems_unsigned16        _pad1;
  rtems_unsigned32        _pad2;
  rtems_unsigned32        _tstate;
  rtems_unsigned32        _pad3;
  rtems_unsigned16        _tbptr;
  rtems_unsigned16        _pad4;
  rtems_unsigned32        _pad5;
  union {
    struct {
      rtems_unsigned16        max_idl;
      rtems_unsigned16        _idlc;
      rtems_unsigned16        brkln;
      rtems_unsigned16        brkec;
      rtems_unsigned16        brkcr;
      rtems_unsigned16        _r_mask;
    } uart;
    struct {
      rtems_unsigned16        _pad0[5];
    } transparent;
  } un;
} m8xxSMCparms_t;

/*
 * Mode register
 */
#define M8xx_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
#define M8xx_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
#define M8xx_SMCMR_PARITY               (1<<9)       /* Enable parity */
#define M8xx_SMCMR_EVEN                 (1<<8)       /* Even parity */
#define M8xx_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
#define M8xx_SMCMR_SM_UART              (2<<4)       /* UART Mode */
#define M8xx_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
#define M8xx_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
#define M8xx_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
#define M8xx_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
#define M8xx_SMCMR_REN                  (1<<0)       /* Enable receiver */

/*
 * Event and mask registers (SMCE, SMCM)
 */
#define M8xx_SMCE_BRKE  (1<<6)
#define M8xx_SMCE_BRK   (1<<4)
#define M8xx_SMCE_BSY   (1<<2)
#define M8xx_SMCE_TX    (1<<1)
#define M8xx_SMCE_RX    (1<<0)

/*
*************************************************************************
*                      Serial Peripheral Interface                      *
*************************************************************************
*/
typedef struct m8xxSPIparms_ {
  rtems_unsigned16        rbase;
  rtems_unsigned16        tbase;
  rtems_unsigned8         rfcr;
  rtems_unsigned8         tfcr;
  rtems_unsigned16        mrblr;
  rtems_unsigned32        _rstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _rbptr;
  rtems_unsigned16        _pad1;
  rtems_unsigned32        _pad2;
  rtems_unsigned32        _tstate;
  rtems_unsigned32        _pad3;
  rtems_unsigned16        _tbptr;
  rtems_unsigned16        _pad4;
  rtems_unsigned32        _pad5;
} m8xxSPIparms_t;

/*
 * Mode register (SPMODE)
 */
#define M8xx_SPMODE_LOOP                (1<<14) /* Local loopback mode */
#define M8xx_SPMODE_CI                  (1<<13) /* Clock invert */
#define M8xx_SPMODE_CP                  (1<<12) /* Clock phase */
#define M8xx_SPMODE_DIV16               (1<<11) /* Divide BRGCLK by 16 */
#define M8xx_SPMODE_REV                 (1<<10) /* Reverse data */
#define M8xx_SPMODE_MASTER              (1<<9)  /* SPI is master */
#define M8xx_SPMODE_EN                  (1<<8)  /* Enable SPI */
#define M8xx_SPMODE_CLEN(x)             ((x)<<4)        /* Character length */
#define M8xx_SPMODE_PM(x)               (x)     /* Prescaler modulus */

/*
 * Mode register (SPCOM)
 */
#define M8xx_SPCOM_STR                  (1<<7)  /* Start transmit */

/*
 * Event and mask registers (SPIE, SPIM)
 */
#define M8xx_SPIE_MME   (1<<5)          /* Multi-master error */
#define M8xx_SPIE_TXE   (1<<4)          /* Tx error */
#define M8xx_SPIE_BSY   (1<<2)          /* Busy condition*/
#define M8xx_SPIE_TXB   (1<<1)          /* Tx buffer */
#define M8xx_SPIE_RXB   (1<<0)          /* Rx buffer */

/*
*************************************************************************
*                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
*************************************************************************
*/
typedef struct m8xxBufferDescriptor_ {
  volatile rtems_unsigned16        status;
  rtems_unsigned16        	   length;
  volatile void           	   *buffer;
} m8xxBufferDescriptor_t;

/*
 * Bits in receive buffer descriptor status word
 */
#define M8xx_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_LAST            (1<<11) /* Ethernet, SPI */
#define M8xx_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
#define M8xx_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
#define M8xx_BD_ADDRESS         (1<<10) /* SCC UART */
#define M8xx_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
#define M8xx_BD_MISS            (1<<8)  /* Ethernet */
#define M8xx_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
#define M8xx_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
#define M8xx_BD_LONG            (1<<5)  /* Ethernet */
#define M8xx_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
#define M8xx_BD_NONALIGNED      (1<<4)  /* Ethernet */
#define M8xx_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
#define M8xx_BD_SHORT           (1<<3)  /* Ethernet */
#define M8xx_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
#define M8xx_BD_CRC_ERROR       (1<<2)  /* Ethernet */
#define M8xx_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_COLLISION       (1<<0)  /* Ethernet */
#define M8xx_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
#define M8xx_BD_MASTER_ERROR    (1<<0)  /* SPI */

/*
 * Bits in transmit buffer descriptor status word
 * Many bits have the same meaning as those in receiver buffer descriptors.
 */
#define M8xx_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
#define M8xx_BD_PAD             (1<<14) /* Ethernet */
#define M8xx_BD_CTS_REPORT      (1<<11) /* SCC UART */
#define M8xx_BD_TX_CRC          (1<<10) /* Ethernet */
#define M8xx_BD_DEFER           (1<<9)  /* Ethernet */
#define M8xx_BD_HEARTBEAT       (1<<8)  /* Ethernet */
#define M8xx_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
#define M8xx_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
#define M8xx_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
#define M8xx_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
#define M8xx_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
#define M8xx_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI */
#define M8xx_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
#define M8xx_BD_CTS_LOST        (1<<0)  /* SCC UART */

/*
*************************************************************************
*                           IDMA Buffer Descriptors                     *
*************************************************************************
*/
typedef struct m8xxIDMABufferDescriptor_ {
  rtems_unsigned16        status;
  rtems_unsigned8         dfcr;       
  rtems_unsigned8         sfcr;       
  rtems_unsigned32        length;
  void                    *source;
  void                    *destination;
} m8xxIDMABufferDescriptor_t;

/*
*************************************************************************
*       RISC Communication Processor Module Command Register (CR)       *
*************************************************************************
*/
#define M8xx_CR_RST             (1<<15) /* Reset communication processor */
#define M8xx_CR_OP_INIT_RX_TX   (0<<8)  /* SCC, SMC UART, SMC GCI, SPI */
#define M8xx_CR_OP_INIT_RX      (1<<8)  /* SCC, SMC UART, SPI */
#define M8xx_CR_OP_INIT_TX      (2<<8)  /* SCC, SMC UART, SPI */
#define M8xx_CR_OP_INIT_HUNT    (3<<8)  /* SCC, SMC UART */
#define M8xx_CR_OP_STOP_TX      (4<<8)  /* SCC, SMC UART */
#define M8xx_CR_OP_GR_STOP_TX   (5<<8)  /* SCC */
#define M8xx_CR_OP_INIT_IDMA    (5<<8)  /* IDMA */
#define M8xx_CR_OP_RESTART_TX   (6<<8)  /* SCC, SMC UART */
#define M8xx_CR_OP_CLOSE_RX_BD  (7<<8)  /* SCC, SMC UART, SPI */
#define M8xx_CR_OP_SET_GRP_ADDR (8<<8)  /* SCC */
#define M8xx_CR_OP_SET_TIMER    (8<<8)  /* Timer */
#define M8xx_CR_OP_GCI_TIMEOUT  (9<<8)  /* SMC GCI */
#define M8xx_CR_OP_RESERT_BCS   (10<<8) /* SCC */
#define M8xx_CR_OP_GCI_ABORT    (10<<8) /* SMC GCI */
#define M8xx_CR_OP_STOP_IDMA    (11<<8) /* IDMA */
#define M8xx_CR_OP_START_DSP    (12<<8) /* DSP */
#define M8xx_CR_OP_INIT_DSP     (13<<8) /* DSP */

#define M8xx_CR_CHAN_SCC1       (0<<4)  /* Channel selection */
#define M8xx_CR_CHAN_I2C        (1<<4)
#define M8xx_CR_CHAN_IDMA1      (1<<4)