mpc8xx.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*
**************************************************************************
**************************************************************************
**                                                                      **
**       MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR         **
**                                                                      **
**                        HARDWARE DECLARATIONS                         **
**                                                                      **
**                                                                      **
**  Submitted By:                                                       **
**                                                                      **
**      W. Eric Norum                                                   **
**      Saskatchewan Accelerator Laboratory                             **
**      University of Saskatchewan                                      **
**      107 North Road                                                  **
**      Saskatoon, Saskatchewan, CANADA                                 **
**      S7N 5C6                                                         **
**                                                                      **
**      [e-mail]                                           **
**                                                                      **
**  Modified for use with the MPC860 (original code was for MC68360)    **
**  by                                                                  **
**      Jay Monkman                                                     **
**      Frasca International, Inc.                                      **
**      906 E. Airport Rd.                                              **
**      Urbana, IL, 61801                                               **
**                                                                      **
**      [e-mail]                                             **
**                                                                      **
**  Modified further for use with the MPC821 by:                        **
**      Andrew Bray <[e-mail]>                                 **
**                                                                      **
**  With some corrections/additions by:                                 **
**      Darlene A. Stewart and                                          **
**      Charles-Antoine Gauthier                                        **
**      Institute for Information Technology                            **
**      National Research Council of Canada                             **
**      Ottawa, ON  K1A 0R6                                             **
**                                                                      **
**      [e-mail]                                      **
**      [e-mail]                                     **
**                                                                      **
**      Corrections/additions:                                          **
**        Copyright (c) 1999, National Research Council of Canada       **
**************************************************************************
**************************************************************************
*/

#ifndef __MPC8xx_h
#define __MPC8xx_h

#ifndef ASM

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Macros for accessing Special Purpose Registers (SPRs)
 */
#define _mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
#define _mfspr(_reg,_spr)   __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) )

#define _isync   __asm__ volatile ("isync\n"::)

/*
 * Core Registers (SPRs)
 */
#define M8xx_DEC        22      /* Decrementer Register */
#define M8xx_DER        149     /* Debug Enable Register */
#define M8xx_ICTRL      158     /* Instruction Support Control Register */
#define M8xx_TBL_WR     284     /* Timebase Lower Write Register */
#define M8xx_TBU_WR     285     /* Timebase Upper Write Register */
#define M8xx_IMMR       638     /* Internal Memory Map Register */

/*
 * Cache Control Registers (SPRs)
 */
#define M8xx_IC_CST     560     /* Instruction Cache Control and Status Register */
#define M8xx_DC_CST     568     /* Data Cache Control and Status Register */
#define M8xx_IC_ADR     561     /* Instruction Cache Address Register */
#define M8xx_DC_ADR     569     /* Data Cache Address Register */
#define M8xx_IC_DAT     562     /* Instruction Cache Data Port Register */
#define M8xx_DC_DAT     570     /* Data Cache Data Port Register */

/*
 * MMU Registers (SPRs)
 */
/* Control Registers */
#define M8xx_MI_CTR     784     /* IMMU Control Register */
#define M8xx_MD_CTR     792     /* DMMU Control Register */
/* TLB Source Registers */
#define M8xx_MI_EPN     787     /* IMMU Effective Page Number Register (EPN) */
#define M8xx_MD_EPN     795     /* DMMU Effective Page Number Register (EPN) */
#define M8xx_MI_TWC     789     /* IMMU Tablewalk Control Register (TWC) */
#define M8xx_MD_TWC     797     /* DMMU Tablewalk Control Register (TWC) */
#define M8xx_MI_RPN     790     /* IMMU Real (physical) Page Number Register (RPN) */
#define M8xx_MD_RPN     798     /* DMMU Real (physical) Page Number Register (RPN) */
/* Tablewalk Assist Registers */
#define M8xx_M_TWB      796     /* MMU Tablewalk Base Register (TWB) */
/* Protection Registers */
#define M8xx_M_CASID    793     /* MMU Current Address Space ID Register */
#define M8xx_MI_AP      786     /* IMMU Access Protection Register */
#define M8xx_MD_AP      794     /* DMMU Access Protection Register */
/* Scratch Register */
#define M8xx_M_TW       799     /* MMU Tablewalk Special Register */
/* Debug Registers */
#define M8xx_MI_CAM     816     /* IMMU CAM Entry Read Register */
#define M8xx_MI_RAM0    817     /* IMMU RAM Entry Read Register 0 */
#define M8xx_MI_RAM1    818     /* IMMU RAM Entry Read Register 1 */
#define M8xx_MD_CAM     824     /* DMMU CAM Entry Read Register */
#define M8xx_MD_RAM0    825     /* DMMU RAM Entry Read Register 0 */
#define M8xx_MD_RAM1    826     /* DMMU RAM Entry Read Register 1 */

#define M8xx_MI_CTR_GPM       (1<<31)
#define M8xx_MI_CTR_PPM       (1<<30)
#define M8xx_MI_CTR_CIDEF     (1<<29)
#define M8xx_MI_CTR_RSV4I     (1<<27)
#define M8xx_MI_CTR_PPCS      (1<<25)
#define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8)   /* ITLB index */

#define M8xx_MD_CTR_GPM       (1<<31)
#define M8xx_MD_CTR_PPM       (1<<30)
#define M8xx_MD_CTR_CIDEF     (1<<29)
#define M8xx_MD_CTR_WTDEF     (1<<28)
#define M8xx_MD_CTR_RSV4D     (1<<27)
#define M8xx_MD_CTR_TWAM      (1<<26)
#define M8xx_MD_CTR_PPCS      (1<<25)
#define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8)   /* DTLB index */

#define M8xx_MI_EPN_VALID     (1<<9)

#define M8xx_MD_EPN_VALID     (1<<9)

#define M8xx_MI_TWC_G         (1<<4)
#define M8xx_MI_TWC_PSS       (0<<2)
#define M8xx_MI_TWC_PS512     (1<<2)
#define M8xx_MI_TWC_PS8       (3<<2)
#define M8xx_MI_TWC_VALID     (1)

#define M8xx_MD_TWC_G         (1<<4)
#define M8xx_MD_TWC_PSS       (0<<2)
#define M8xx_MD_TWC_PS512     (1<<2)
#define M8xx_MD_TWC_PS8       (3<<2)
#define M8xx_MD_TWC_WT        (1<<1)
#define M8xx_MD_TWC_VALID     (1)

#define M8xx_MI_RPN_F         (0xf<<4)
#define M8xx_MI_RPN_16K       (1<<3)
#define M8xx_MI_RPN_SHARED    (1<<2)
#define M8xx_MI_RPN_CI        (1<<1)
#define M8xx_MI_RPN_VALID     (1)

#define M8xx_MD_RPN_CHANGE    (1<<8)
#define M8xx_MD_RPN_F         (0xf<<4)
#define M8xx_MD_RPN_16K       (1<<3)
#define M8xx_MD_RPN_SHARED    (1<<2)
#define M8xx_MD_RPN_CI        (1<<1)
#define M8xx_MD_RPN_VALID     (1)

#define M8xx_MI_AP_Kp         (1)

#define M8xx_MD_AP_Kp         (1)

#define M8xx_CACHE_CMD_SFWT          (0x1<<24)
#define M8xx_CACHE_CMD_ENABLE        (0x2<<24)
#define M8xx_CACHE_CMD_CFWT          (0x3<<24)
#define M8xx_CACHE_CMD_DISABLE       (0x4<<24)
#define M8xx_CACHE_CMD_STLES         (0x5<<24)
#define M8xx_CACHE_CMD_LLCB          (0x6<<24)
#define M8xx_CACHE_CMD_CLES          (0x7<<24)
#define M8xx_CACHE_CMD_UNLOCK        (0x8<<24)
#define M8xx_CACHE_CMD_UNLOCKALL     (0xa<<24)
#define M8xx_CACHE_CMD_INVALIDATE    (0xc<<24)
#define M8xx_CACHE_CMD_FLUSH         (0xe<<24)

/*
*************************************************************************
*                         REGISTER SUBBLOCKS                            *
*************************************************************************
*/

/*
 * Memory controller registers
 */
typedef struct m8xxMEMCRegisters_ {
  rtems_unsigned32        _br;
  rtems_unsigned32        _or;    /* Used to be called 'or'; reserved ANSI C++ keyword */
} m8xxMEMCRegisters_t;

/*
 * Serial Communications Controller registers
 */
typedef struct m8xxSCCRegisters_ {
  rtems_unsigned32        gsmr_l;
  rtems_unsigned32        gsmr_h;
  rtems_unsigned16        psmr;
  rtems_unsigned16        _pad0;
  rtems_unsigned16        todr;
  rtems_unsigned16        dsr;
  rtems_unsigned16        scce;
  rtems_unsigned16        _pad1;
  rtems_unsigned16        sccm;
  rtems_unsigned8         _pad2;
  rtems_unsigned8         sccs;
  rtems_unsigned32        _pad3[2];
} m8xxSCCRegisters_t;

/*
 * Serial Management Controller registers
 */
typedef struct m8xxSMCRegisters_ {
  rtems_unsigned16        _pad0;
  rtems_unsigned16        smcmr;
  rtems_unsigned16        _pad1;
  rtems_unsigned8         smce;
  rtems_unsigned8         _pad2;
  rtems_unsigned16        _pad3;
  rtems_unsigned8         smcm;
  rtems_unsigned8         _pad4;
  rtems_unsigned32        _pad5;
} m8xxSMCRegisters_t;

/*
 * Fast Ethernet Controller registers (Only on MPC8xxT)
 */
typedef struct m8xxFECRegisters_ {
  rtems_unsigned32    addr_low;
  rtems_unsigned32    addr_high;
  rtems_unsigned32    hash_table_high;
  rtems_unsigned32    hash_table_low;
  rtems_unsigned32    r_des_start;
  rtems_unsigned32    x_des_start;
  rtems_unsigned32    r_buf_size;
  rtems_unsigned32    _pad0[9];
  rtems_unsigned32    ecntrl;
  rtems_unsigned32    ievent;
  rtems_unsigned32    imask;
  rtems_unsigned32    ivec;
  rtems_unsigned32    r_des_active;
  rtems_unsigned32    x_des_active;
  rtems_unsigned32    _pad1[10];
  rtems_unsigned32    mii_data;
  rtems_unsigned32    mii_speed;
  rtems_unsigned32    _pad2[17];
  rtems_unsigned32    r_bound;
  rtems_unsigned32    r_fstart;
  rtems_unsigned32    _pad3[6];
  rtems_unsigned32    x_fstart;
  rtems_unsigned32    _pad4[17];
  rtems_unsigned32    fun_code;
  rtems_unsigned32    _pad5[3];
  rtems_unsigned32    r_cntrl;
  rtems_unsigned32    r_hash;
  rtems_unsigned32    _pad6[14];
  rtems_unsigned32    x_cntrl;
  rtems_unsigned32    _pad7[30];

} m8xxFECRegisters_t;

#define M8xx_FEC_IEVENT_HBERR  (1 << 31)
#define M8xx_FEC_IEVENT_BABR   (1 << 30)
#define M8xx_FEC_IEVENT_BABT   (1 << 29)
#define M8xx_FEC_IEVENT_GRA    (1 << 28)
#define M8xx_FEC_IEVENT_TFINT  (1 << 27)
#define M8xx_FEC_IEVENT_TXB    (1 << 26)
#define M8xx_FEC_IEVENT_RFINT  (1 << 25)
#define M8xx_FEC_IEVENT_RXB    (1 << 24)
#define M8xx_FEC_IEVENT_MII    (1 << 23)
#define M8xx_FEC_IEVENT_EBERR  (1 << 22)
#define M8xx_FEC_IMASK_HBEEN   (1 << 31)
#define M8xx_FEC_IMASK_BREEN   (1 << 30)
#define M8xx_FEC_IMASK_BTEN    (1 << 29)
#define M8xx_FEC_IMASK_GRAEN   (1 << 28)
#define M8xx_FEC_IMASK_TFIEN   (1 << 27)
#define M8xx_FEC_IMASK_TBIEN   (1 << 26)
#define M8xx_FEC_IMASK_RFIEN   (1 << 25)
#define M8xx_FEC_IMASK_RBIEN   (1 << 24)
#define M8xx_FEC_IMASK_MIIEN   (1 << 23)
#define M8xx_FEC_IMASK_EBERREN (1 << 22)

/*
*************************************************************************
*                         Miscellaneous Parameters                      *
*************************************************************************
*/
typedef struct m8xxMiscParms_ {
  rtems_unsigned16        rev_num;
  rtems_unsigned16        _res1;
  rtems_unsigned32        _res2;
  rtems_unsigned32        _res3;
} m8xxMiscParms_t;

/*
*************************************************************************
*                              RISC Timers                              *
*************************************************************************
*/
typedef struct m8xxTimerParms_ {
  rtems_unsigned16        tm_base;
  rtems_unsigned16        _tm_ptr;
  rtems_unsigned16        _r_tmr;
  rtems_unsigned16        _r_tmv;
  rtems_unsigned32        tm_cmd;
  rtems_unsigned32        tm_cnt;
} m8xxTimerParms_t;

/*
 * RISC Controller Configuration Register (RCCR)
 * All other bits in this register are reserved.
 */
#define M8xx_RCCR_TIME          (1<<15)    /* Enable timer */
#define M8xx_RCCR_TIMEP(x)      ((x)<<8)   /* Timer period */
#define M8xx_RCCR_DR1M          (1<<7)     /* IDMA Rqst 1 Mode */
#define M8xx_RCCR_DR0M          (1<<6)     /* IDMA Rqst 0 Mode */
#define M8xx_RCCR_DRQP(x)       ((x)<<4)   /* IDMA Rqst Priority */
#define M8xx_RCCR_EIE           (1<<3)     /* External Interrupt Enable */
#define M8xx_RCCR_SCD           (1<<2)     /* Scheduler Configuration */
#define M8xx_RCCR_ERAM(x)       (x)        /* Enable RAM Microcode */

/*
 * Command register
 * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command.
 */
#define M8xx_TM_CMD_V           (1<<31)         /* Set to enable timer */
#define M8xx_TM_CMD_R           (1<<30)         /* Set for automatic restart */
#define M8xx_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
#define M8xx_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
#define M8xx_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */

/*
*************************************************************************
*                               DMA Controllers                         *
*************************************************************************
*/
typedef struct m8xxIDMAparms_ {
  rtems_unsigned16        ibase;
  rtems_unsigned16        dcmr;
  rtems_unsigned32        _sapr;
  rtems_unsigned32        _dapr;
  rtems_unsigned16        ibptr;
  rtems_unsigned16        _write_sp;
  rtems_unsigned32        _s_byte_c;
  rtems_unsigned32        _d_byte_c;
  rtems_unsigned32        _s_state;
  rtems_unsigned32        _itemp[4];
  rtems_unsigned32        _sr_mem;
  rtems_unsigned16        _read_sp;
  rtems_unsigned16        _res0;
  rtems_unsigned16        _res1;
  rtems_unsigned16        _res2;
  rtems_unsigned32        _d_state;
} m8xxIDMAparms_t;


/*
*************************************************************************
*                               DSP                                     *
*************************************************************************
*/
typedef struct m8xxDSPparms_ {
  rtems_unsigned32        fdbase;
  rtems_unsigned32        _fd_ptr;
  rtems_unsigned32        _dstate;
  rtems_unsigned32        _pad0;
  rtems_unsigned16        _dstatus;
  rtems_unsigned16        _i;
  rtems_unsigned16        _tap;
  rtems_unsigned16        _cbase;
  rtems_unsigned16        _pad1;
  rtems_unsigned16        _xptr;