sh7750_regs.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define SH7750_PCR_A5PCW_0    0x0000 /*    0 waits inserted */
#define SH7750_PCR_A5PCW_15   0x4000 /*    15 waits inserted */
#define SH7750_PCR_A5PCW_30   0x8000 /*    30 waits inserted */
#define SH7750_PCR_A5PCW_50   0xC000 /*    50 waits inserted */

#define SH7750_PCR_A6PCW      0x3000 /* Area 6 PCMCIA Wait - Number of wait
                                        states to be added to the number of
                                        waits specified by WCR2 in a low-speed
                                        PCMCIA wait cycle */
#define SH7750_PCR_A6PCW_0    0x0000 /*    0 waits inserted */
#define SH7750_PCR_A6PCW_15   0x1000 /*    15 waits inserted */
#define SH7750_PCR_A6PCW_30   0x2000 /*    30 waits inserted */
#define SH7750_PCR_A6PCW_50   0x3000 /*    50 waits inserted */

#define SH7750_PCR_A5TED      0x0E00 /* Area 5 Address-OE\/WE\ Assertion Delay,
                                        delay time from address output to
                                        OE\/WE\ assertion on the connected
                                        PCMCIA interface */
#define SH7750_PCR_A5TED_S    9
#define SH7750_PCR_A6TED      0x01C0 /* Area 6 Address-OE\/WE\ Assertion Delay*/
#define SH7750_PCR_A6TED_S    6

#define SH7750_PCR_TED_0WS    0     /* 0 Waits inserted */
#define SH7750_PCR_TED_1WS    1     /* 1 Waits inserted */
#define SH7750_PCR_TED_2WS    2     /* 2 Waits inserted */
#define SH7750_PCR_TED_3WS    3     /* 3 Waits inserted */
#define SH7750_PCR_TED_6WS    4     /* 6 Waits inserted */
#define SH7750_PCR_TED_9WS    5     /* 9 Waits inserted */
#define SH7750_PCR_TED_12WS   6     /* 12 Waits inserted */
#define SH7750_PCR_TED_15WS   7     /* 15 Waits inserted */

#define SH7750_PCR_A5TEH      0x0038 /* Area 5 OE\/WE\ Negation Address delay,
                                        address hold delay time from OE\/WE\
                                        negation in a write on the connected
                                        PCMCIA interface */
#define SH7750_PCR_A5TEH_S    3

#define SH7750_PCR_A6TEH      0x0007 /* Area 6 OE\/WE\ Negation Address delay*/
#define SH7750_PCR_A6TEH_S    0

#define SH7750_PCR_TEH_0WS    0     /* 0 Waits inserted */
#define SH7750_PCR_TEH_1WS    1     /* 1 Waits inserted */
#define SH7750_PCR_TEH_2WS    2     /* 2 Waits inserted */
#define SH7750_PCR_TEH_3WS    3     /* 3 Waits inserted */
#define SH7750_PCR_TEH_6WS    4     /* 6 Waits inserted */
#define SH7750_PCR_TEH_9WS    5     /* 9 Waits inserted */
#define SH7750_PCR_TEH_12WS   6     /* 12 Waits inserted */
#define SH7750_PCR_TEH_15WS   7     /* 15 Waits inserted */

/* Refresh Timer Control/Status Register (half) - RTSCR */
#define SH7750_RTCSR_REGOFS   0x80001C /* offset */
#define SH7750_RTCSR          SH7750_P4_REG32(SH7750_RTCSR_REGOFS)
#define SH7750_RTCSR_A7       SH7750_A7_REG32(SH7750_RTCSR_REGOFS)

#define SH7750_RTCSR_KEY      0xA500 /* RTCSR write key */
#define SH7750_RTCSR_CMF      0x0080 /* Compare-Match Flag (indicates a
                                        match between the refresh timer
                                        counter and refresh time constant) */
#define SH7750_RTCSR_CMIE     0x0040 /* Compare-Match Interrupt Enable */
#define SH7750_RTCSR_CKS      0x0038 /* Refresh Counter Clock Selects */
#define SH7750_RTCSR_CKS_DIS          0x0000 /* Clock Input Disabled */
#define SH7750_RTCSR_CKS_CKIO_DIV4    0x0008 /* Bus Clock / 4 */
#define SH7750_RTCSR_CKS_CKIO_DIV16   0x0010 /* Bus Clock / 16 */
#define SH7750_RTCSR_CKS_CKIO_DIV64   0x0018 /* Bus Clock / 64 */
#define SH7750_RTCSR_CKS_CKIO_DIV256  0x0020 /* Bus Clock / 256 */
#define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */
#define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */
#define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */

#define SH7750_RTCSR_OVF      0x0004 /* Refresh Count Overflow Flag */
#define SH7750_RTCSR_OVIE     0x0002 /* Refresh Count Overflow Interrupt
                                        Enable */
#define SH7750_RTCSR_LMTS     0x0001 /* Refresh Count Overflow Limit Select */
#define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */
#define SH7750_RTCSR_LMTS_512  0x0001 /* Count Limit is 512 */

/* Refresh Timer Counter (half) - RTCNT */
#define SH7750_RTCNT_REGOFS   0x800020 /* offset */
#define SH7750_RTCNT          SH7750_P4_REG32(SH7750_RTCNT_REGOFS)
#define SH7750_RTCNT_A7       SH7750_A7_REG32(SH7750_RTCNT_REGOFS)

#define SH7750_RTCNT_KEY      0xA500 /* RTCNT write key */

/* Refresh Time Constant Register (half) - RTCOR */
#define SH7750_RTCOR_REGOFS   0x800024 /* offset */
#define SH7750_RTCOR          SH7750_P4_REG32(SH7750_RTCOR_REGOFS)
#define SH7750_RTCOR_A7       SH7750_A7_REG32(SH7750_RTCOR_REGOFS)

#define SH7750_RTCOR_KEY      0xA500 /* RTCOR write key */

/* Refresh Count Register (half) - RFCR */
#define SH7750_RFCR_REGOFS    0x800028 /* offset */
#define SH7750_RFCR           SH7750_P4_REG32(SH7750_RFCR_REGOFS)
#define SH7750_RFCR_A7        SH7750_A7_REG32(SH7750_RFCR_REGOFS)

#define SH7750_RFCR_KEY       0xA400 /* RFCR write key */

/*
 * Direct Memory Access Controller (DMAC)
 */

/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
#define SH7750_SAR_REGOFS(n)  (0xA00000 + ((n)*16)) /* offset */
#define SH7750_SAR(n)         SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
#define SH7750_SAR_A7(n)      SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
#define SH7750_SAR0           SH7750_SAR(0)
#define SH7750_SAR1           SH7750_SAR(1)
#define SH7750_SAR2           SH7750_SAR(2)
#define SH7750_SAR3           SH7750_SAR(3)
#define SH7750_SAR0_A7        SH7750_SAR_A7(0)
#define SH7750_SAR1_A7        SH7750_SAR_A7(1)
#define SH7750_SAR2_A7        SH7750_SAR_A7(2)
#define SH7750_SAR3_A7        SH7750_SAR_A7(3)

/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
#define SH7750_DAR_REGOFS(n)  (0xA00004 + ((n)*16)) /* offset */
#define SH7750_DAR(n)         SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
#define SH7750_DAR_A7(n)      SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
#define SH7750_DAR0           SH7750_DAR(0)
#define SH7750_DAR1           SH7750_DAR(1)
#define SH7750_DAR2           SH7750_DAR(2)
#define SH7750_DAR3           SH7750_DAR(3)
#define SH7750_DAR0_A7        SH7750_DAR_A7(0)
#define SH7750_DAR1_A7        SH7750_DAR_A7(1)
#define SH7750_DAR2_A7        SH7750_DAR_A7(2)
#define SH7750_DAR3_A7        SH7750_DAR_A7(3)

/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
#define SH7750_DMATCR_REGOFS(n)  (0xA00008 + ((n)*16)) /* offset */
#define SH7750_DMATCR(n)      SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
#define SH7750_DMATCR_A7(n)   SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
#define SH7750_DMATCR0_P4     SH7750_DMATCR(0)
#define SH7750_DMATCR1_P4     SH7750_DMATCR(1)
#define SH7750_DMATCR2_P4     SH7750_DMATCR(2)
#define SH7750_DMATCR3_P4     SH7750_DMATCR(3)
#define SH7750_DMATCR0_A7     SH7750_DMATCR_A7(0)
#define SH7750_DMATCR1_A7     SH7750_DMATCR_A7(1)
#define SH7750_DMATCR2_A7     SH7750_DMATCR_A7(2)
#define SH7750_DMATCR3_A7     SH7750_DMATCR_A7(3)

/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
#define SH7750_CHCR_REGOFS(n)  (0xA0000C + ((n)*16)) /* offset */
#define SH7750_CHCR(n)        SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR_A7(n)     SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR0          SH7750_CHCR(0)
#define SH7750_CHCR1          SH7750_CHCR(1)
#define SH7750_CHCR2          SH7750_CHCR(2)
#define SH7750_CHCR3          SH7750_CHCR(3)
#define SH7750_CHCR0_A7       SH7750_CHCR_A7(0)
#define SH7750_CHCR1_A7       SH7750_CHCR_A7(1)
#define SH7750_CHCR2_A7       SH7750_CHCR_A7(2)
#define SH7750_CHCR3_A7       SH7750_CHCR_A7(3)

#define SH7750_CHCR_SSA       0xE0000000 /* Source Address Space Attribute */
#define SH7750_CHCR_SSA_PCMCIA  0x00000000 /* Reserved in PCMCIA access */
#define SH7750_CHCR_SSA_DYNBSZ  0x20000000 /* Dynamic Bus Sizing I/O space */
#define SH7750_CHCR_SSA_IO8     0x40000000 /* 8-bit I/O space */
#define SH7750_CHCR_SSA_IO16    0x60000000 /* 16-bit I/O space */
#define SH7750_CHCR_SSA_CMEM8   0x80000000 /* 8-bit common memory space */
#define SH7750_CHCR_SSA_CMEM16  0xA0000000 /* 16-bit common memory space */
#define SH7750_CHCR_SSA_AMEM8   0xC0000000 /* 8-bit attribute memory space */
#define SH7750_CHCR_SSA_AMEM16  0xE0000000 /* 16-bit attribute memory space */

#define SH7750_CHCR_STC       0x10000000 /* Source Address Wait Control Select,
                                            specifies CS5 or CS6 space wait
                                            control for PCMCIA access */

#define SH7750_CHCR_DSA       0x0E000000 /* Source Address Space Attribute */
#define SH7750_CHCR_DSA_PCMCIA  0x00000000 /* Reserved in PCMCIA access */
#define SH7750_CHCR_DSA_DYNBSZ  0x02000000 /* Dynamic Bus Sizing I/O space */
#define SH7750_CHCR_DSA_IO8     0x04000000 /* 8-bit I/O space */
#define SH7750_CHCR_DSA_IO16    0x06000000 /* 16-bit I/O space */
#define SH7750_CHCR_DSA_CMEM8   0x08000000 /* 8-bit common memory space */
#define SH7750_CHCR_DSA_CMEM16  0x0A000000 /* 16-bit common memory space */
#define SH7750_CHCR_DSA_AMEM8   0x0C000000 /* 8-bit attribute memory space */
#define SH7750_CHCR_DSA_AMEM16  0x0E000000 /* 16-bit attribute memory space */

#define SH7750_CHCR_DTC       0x01000000 /* Destination Address Wait Control
                                            Select, specifies CS5 or CS6 
                                            space wait control for PCMCIA
                                            access */

#define SH7750_CHCR_DS        0x00080000 /* DREQ\ Select : */
#define SH7750_CHCR_DS_LOWLVL 0x00000000 /*     Low Level Detection */
#define SH7750_CHCR_DS_FALL   0x00080000 /*     Falling Edge Detection */

#define SH7750_CHCR_RL        0x00040000 /* Request Check Level: */
#define SH7750_CHCR_RL_ACTH   0x00000000 /*     DRAK is an active high out */
#define SH7750_CHCR_RL_ACTL   0x00040000 /*     DRAK is an active low out */

#define SH7750_CHCR_AM        0x00020000 /* Acknowledge Mode: */
#define SH7750_CHCR_AM_RD     0x00000000 /*     DACK is output in read cycle */
#define SH7750_CHCR_AM_WR     0x00020000 /*     DACK is output in write cycle*/

#define SH7750_CHCR_AL        0x00010000 /* Acknowledge Level: */
#define SH7750_CHCR_AL_ACTH   0x00000000 /*     DACK is an active high out */
#define SH7750_CHCR_AL_ACTL   0x00010000 /*     DACK is an active low out */

#define SH7750_CHCR_DM        0x0000C000 /* Destination Address Mode: */
#define SH7750_CHCR_DM_FIX    0x00000000 /*     Destination Addr Fixed */
#define SH7750_CHCR_DM_INC    0x00004000 /*     Destination Addr Incremented */
#define SH7750_CHCR_DM_DEC    0x00008000 /*     Destination Addr Decremented */

#define SH7750_CHCR_SM        0x00003000 /* Source Address Mode: */
#define SH7750_CHCR_SM_FIX    0x00000000 /*     Source Addr Fixed */
#define SH7750_CHCR_SM_INC    0x00001000 /*     Source Addr Incremented */
#define SH7750_CHCR_SM_DEC    0x00002000 /*     Source Addr Decremented */

#define SH7750_CHCR_RS        0x00000F00 /* Request Source Select: */
#define SH7750_CHCR_RS_ER_DA_EA_TO_EA   0x000 /* External Request, Dual Address
                                                 Mode (External Addr Space->
                                                 External Addr Space) */
#define SH7750_CHCR_RS_ER_SA_EA_TO_ED   0x200 /* External Request, Single
                                                 Address Mode (External Addr
                                                 Space -> External Device) */
#define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300 /* External Request, Single
                                                 Address Mode, (External 
                                                 Device -> External Addr 
                                                 Space)*/
#define SH7750_CHCR_RS_AR_EA_TO_EA      0x400 /* Auto-Request (External Addr
                                                 Space -> External Addr Space)*/

#define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500 /* Auto-Request (External Addr
                                                 Space -> On-chip Peripheral
                                                 Module) */
#define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600 /* Auto-Request (On-chip 
                                                 Peripheral Module ->
                                                 External Addr Space */
#define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800 /* SCI Transmit-Data-Empty intr
                                                 transfer request (external
                                                 address space -> SCTDR1) */
#define SH7750_CHCR_RS_SCIRX_SC_TO_EA   0x900 /* SCI Receive-Data-Full intr
                                                 transfer request (SCRDR1 ->
                                                 External Addr Space) */
#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC  0xA00 /* SCIF Transmit-Data-Empty intr
                                                 transfer request (external
                                                 address space -> SCFTDR1) */ 
#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA  0xB00 /* SCIF Receive-Data-Full intr
                                                 transfer request (SCFRDR2 ->
                                                 External Addr Space) */
#define SH7750_CHCR_RS_TMU2_EA_TO_EA    0xC00 /* TMU