sh7750_regs.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define SH7750_BCR2_A3SZ_S    6
#define SH7750_BCR2_A2SZ      0x0030 /* Area 2 Bus Width */
#define SH7750_BCR2_A2SZ_S    4
#define SH7750_BCR2_A1SZ      0x000C /* Area 1 Bus Width */
#define SH7750_BCR2_A1SZ_S    2
#define SH7750_BCR2_SZ_64     0 /* 64 bits */
#define SH7750_BCR2_SZ_8      1 /* 8 bits */
#define SH7750_BCR2_SZ_16     2 /* 16 bits */
#define SH7750_BCR2_SZ_32     3 /* 32 bits */
#define SH7750_BCR2_PORTEN    0x0001 /* Port Function Enable :
                                          0 - D51-D32 are not used as a port
                                          1 - D51-D32 are used as a port */

/* Wait Control Register 1 - WCR1 */
#define SH7750_WCR1_REGOFS    0x800008 /* offset */
#define SH7750_WCR1           SH7750_P4_REG32(SH7750_WCR1_REGOFS)
#define SH7750_WCR1_A7        SH7750_A7_REG32(SH7750_WCR1_REGOFS)
#define SH7750_WCR1_DMAIW     0x70000000 /* DACK Device Inter-Cycle Idle
                                            specification */
#define SH7750_WCR1_DMAIW_S   28
#define SH7750_WCR1_A6IW      0x07000000 /* Area 6 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A6IW_S    24
#define SH7750_WCR1_A5IW      0x00700000 /* Area 5 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A5IW_S    20
#define SH7750_WCR1_A4IW      0x00070000 /* Area 4 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A4IW_S    16
#define SH7750_WCR1_A3IW      0x00007000 /* Area 3 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A3IW_S    12
#define SH7750_WCR1_A2IW      0x00000700 /* Area 2 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A2IW_S    8
#define SH7750_WCR1_A1IW      0x00000070 /* Area 1 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A1IW_S    4
#define SH7750_WCR1_A0IW      0x00000007 /* Area 0 Inter-Cycle Idle spec. */
#define SH7750_WCR1_A0IW_S    0

/* Wait Control Register 2 - WCR2 */
#define SH7750_WCR2_REGOFS    0x80000C /* offset */
#define SH7750_WCR2           SH7750_P4_REG32(SH7750_WCR2_REGOFS)
#define SH7750_WCR2_A7        SH7750_A7_REG32(SH7750_WCR2_REGOFS)

#define SH7750_WCR2_A6W       0xE0000000 /* Area 6 Wait Control */
#define SH7750_WCR2_A6W_S     29
#define SH7750_WCR2_A6B       0x1C000000 /* Area 6 Burst Pitch */
#define SH7750_WCR2_A6B_S     26
#define SH7750_WCR2_A5W       0x03800000 /* Area 5 Wait Control */
#define SH7750_WCR2_A5W_S     23
#define SH7750_WCR2_A5B       0x00700000 /* Area 5 Burst Pitch */
#define SH7750_WCR2_A5B_S     20
#define SH7750_WCR2_A4W       0x000E0000 /* Area 4 Wait Control */
#define SH7750_WCR2_A4W_S     17
#define SH7750_WCR2_A3W       0x0000E000 /* Area 3 Wait Control */
#define SH7750_WCR2_A3W_S     13
#define SH7750_WCR2_A2W       0x00000E00 /* Area 2 Wait Control */
#define SH7750_WCR2_A2W_S     9
#define SH7750_WCR2_A1W       0x000001C0 /* Area 1 Wait Control */
#define SH7750_WCR2_A1W_S     6
#define SH7750_WCR2_A0W       0x00000038 /* Area 0 Wait Control */
#define SH7750_WCR2_A0W_S     3
#define SH7750_WCR2_A0B       0x00000007 /* Area 0 Burst Pitch */
#define SH7750_WCR2_A0B_S     0

#define SH7750_WCR2_WS0       0   /* 0 wait states inserted */
#define SH7750_WCR2_WS1       1   /* 1 wait states inserted */
#define SH7750_WCR2_WS2       2   /* 2 wait states inserted */
#define SH7750_WCR2_WS3       3   /* 3 wait states inserted */
#define SH7750_WCR2_WS6       4   /* 6 wait states inserted */
#define SH7750_WCR2_WS9       5   /* 9 wait states inserted */
#define SH7750_WCR2_WS12      6   /* 12 wait states inserted */
#define SH7750_WCR2_WS15      7   /* 15 wait states inserted */

#define SH7750_WCR2_BPWS0     0   /* 0 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS1     1   /* 1 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS2     2   /* 2 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS3     3   /* 3 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS4     4   /* 4 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS5     5   /* 5 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS6     6   /* 6 wait states inserted from 2nd access */
#define SH7750_WCR2_BPWS7     7   /* 7 wait states inserted from 2nd access */

/* DRAM CAS\ Assertion Delay (area 3,2) */
#define SH7750_WCR2_DRAM_CAS_ASW1   0   /* 1 cycle */
#define SH7750_WCR2_DRAM_CAS_ASW2   1   /* 2 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW3   2   /* 3 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW4   3   /* 4 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW7   4   /* 7 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW10  5   /* 10 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW13  6   /* 13 cycles */
#define SH7750_WCR2_DRAM_CAS_ASW16  7   /* 16 cycles */

/* SDRAM CAS\ Latency Cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT1  1   /* 1 cycle */
#define SH7750_WCR2_SDRAM_CAS_LAT2  2   /* 2 cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT3  3   /* 3 cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT4  4   /* 4 cycles */
#define SH7750_WCR2_SDRAM_CAS_LAT5  5   /* 5 cycles */

/* Wait Control Register 3 - WCR3 */
#define SH7750_WCR3_REGOFS    0x800010 /* offset */
#define SH7750_WCR3           SH7750_P4_REG32(SH7750_WCR3_REGOFS)
#define SH7750_WCR3_A7        SH7750_A7_REG32(SH7750_WCR3_REGOFS)

#define SH7750_WCR3_A6S       0x04000000 /* Area 6 Write Strobe Setup time */
#define SH7750_WCR3_A6H       0x03000000 /* Area 6 Data Hold Time */
#define SH7750_WCR3_A6H_S     24
#define SH7750_WCR3_A5S       0x00400000 /* Area 5 Write Strobe Setup time */
#define SH7750_WCR3_A5H       0x00300000 /* Area 5 Data Hold Time */
#define SH7750_WCR3_A5H_S     20
#define SH7750_WCR3_A4S       0x00040000 /* Area 4 Write Strobe Setup time */
#define SH7750_WCR3_A4H       0x00030000 /* Area 4 Data Hold Time */
#define SH7750_WCR3_A4H_S     16
#define SH7750_WCR3_A3S       0x00004000 /* Area 3 Write Strobe Setup time */
#define SH7750_WCR3_A3H       0x00003000 /* Area 3 Data Hold Time */
#define SH7750_WCR3_A3H_S     12
#define SH7750_WCR3_A2S       0x00000400 /* Area 2 Write Strobe Setup time */
#define SH7750_WCR3_A2H       0x00000300 /* Area 2 Data Hold Time */
#define SH7750_WCR3_A2H_S     8
#define SH7750_WCR3_A1S       0x00000040 /* Area 1 Write Strobe Setup time */
#define SH7750_WCR3_A1H       0x00000030 /* Area 1 Data Hold Time */
#define SH7750_WCR3_A1H_S     4
#define SH7750_WCR3_A0S       0x00000004 /* Area 0 Write Strobe Setup time */
#define SH7750_WCR3_A0H       0x00000003 /* Area 0 Data Hold Time */
#define SH7750_WCR3_A0H_S     0

#define SH7750_WCR3_DHWS_0    0  /* 0 wait states data hold time */
#define SH7750_WCR3_DHWS_1    1  /* 1 wait states data hold time */
#define SH7750_WCR3_DHWS_2    2  /* 2 wait states data hold time */
#define SH7750_WCR3_DHWS_3    3  /* 3 wait states data hold time */

#define SH7750_MCR_REGOFS     0x800014 /* offset */
#define SH7750_MCR            SH7750_P4_REG32(SH7750_MCR_REGOFS)
#define SH7750_MCR_A7         SH7750_A7_REG32(SH7750_MCR_REGOFS)

#define SH7750_MCR_RASD       0x80000000 /* RAS Down mode */
#define SH7750_MCR_MRSET      0x40000000 /* SDRAM Mode Register Set */
#define SH7750_MCR_PALL       0x00000000 /* SDRAM Precharge All cmd. Mode */
#define SH7750_MCR_TRC        0x38000000 /* RAS Precharge Time at End of
                                            Refresh: */
#define SH7750_MCR_TRC_0      0x00000000 /*    0 */
#define SH7750_MCR_TRC_3      0x08000000 /*    3 */
#define SH7750_MCR_TRC_6      0x10000000 /*    6 */
#define SH7750_MCR_TRC_9      0x18000000 /*    9 */
#define SH7750_MCR_TRC_12     0x20000000 /*    12 */
#define SH7750_MCR_TRC_15     0x28000000 /*    15 */
#define SH7750_MCR_TRC_18     0x30000000 /*    18 */
#define SH7750_MCR_TRC_21     0x38000000 /*    21 */

#define SH7750_MCR_TCAS       0x00800000 /* CAS Negation Period */
#define SH7750_MCR_TCAS_1     0x00000000 /*    1 */
#define SH7750_MCR_TCAS_2     0x00800000 /*    2 */

#define SH7750_MCR_TPC        0x00380000 /* DRAM: RAS Precharge Period 
                                            SDRAM: minimum number of cycles
                                            until the next bank active cmd
                                            is output after precharging */
#define SH7750_MCR_TPC_S      19
#define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */
#define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */
#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ 
#define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */
#define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */
#define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */
#define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */
#define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */

#define SH7750_MCR_RCD        0x00030000 /* DRAM: RAS-CAS Assertion Delay time
                                            SDRAM: bank active-read/write cmd
                                            delay time */
#define SH7750_MCR_RCD_DRAM_2  0x00000000 /* DRAM delay 2 clocks */
#define SH7750_MCR_RCD_DRAM_3  0x00010000 /* DRAM delay 3 clocks */
#define SH7750_MCR_RCD_DRAM_4  0x00020000 /* DRAM delay 4 clocks */
#define SH7750_MCR_RCD_DRAM_5  0x00030000 /* DRAM delay 5 clocks */
#define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */
#define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */
#define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */

#define SH7750_MCR_TRWL       0x0000E000 /* SDRAM Write Precharge Delay */
#define SH7750_MCR_TRWL_1     0x00000000 /*    1 */
#define SH7750_MCR_TRWL_2     0x00002000 /*    2 */
#define SH7750_MCR_TRWL_3     0x00004000 /*    3 */
#define SH7750_MCR_TRWL_4     0x00006000 /*    4 */
#define SH7750_MCR_TRWL_5     0x00008000 /*    5 */

#define SH7750_MCR_TRAS       0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS
                                            asserting period
                                            SDRAM: Command interval after
                                            synchronous DRAM refresh */
#define SH7750_MCR_TRAS_DRAM_2         0x00000000 /* 2 */
#define SH7750_MCR_TRAS_DRAM_3         0x00000400 /* 3 */
#define SH7750_MCR_TRAS_DRAM_4         0x00000800 /* 4 */
#define SH7750_MCR_TRAS_DRAM_5         0x00000C00 /* 5 */
#define SH7750_MCR_TRAS_DRAM_6         0x00001000 /* 6 */
#define SH7750_MCR_TRAS_DRAM_7         0x00001400 /* 7 */
#define SH7750_MCR_TRAS_DRAM_8         0x00001800 /* 8 */
#define SH7750_MCR_TRAS_DRAM_9         0x00001C00 /* 9 */

#define SH7750_MCR_TRAS_SDRAM_TRC_4    0x00000000 /* 4 + TRC */
#define SH7750_MCR_TRAS_SDRAM_TRC_5    0x00000400 /* 5 + TRC */
#define SH7750_MCR_TRAS_SDRAM_TRC_6    0x00000800 /* 6 + TRC */
#define SH7750_MCR_TRAS_SDRAM_TRC_7    0x00000C00 /* 7 + TRC */
#define SH7750_MCR_TRAS_SDRAM_TRC_8    0x00001000 /* 8 + TRC */
#define SH7750_MCR_TRAS_SDRAM_TRC_9    0x00001400 /* 9 + TRC */
#define SH7750_MCR_TRAS_SDRAM_TRC_10   0x00001800 /* 10 + TRC */
#define SH7750_MCR_TRAS_SDRAM_TRC_11   0x00001C00 /* 11 + TRC */

#define SH7750_MCR_BE         0x00000200 /* Burst Enable */
#define SH7750_MCR_SZ         0x00000180 /* Memory Data Size */
#define SH7750_MCR_SZ_64      0x00000000 /*    64 bits */
#define SH7750_MCR_SZ_16      0x00000100 /*    16 bits */
#define SH7750_MCR_SZ_32      0x00000180 /*    32 bits */

#define SH7750_MCR_AMX        0x00000078 /* Address Multiplexing */
#define SH7750_MCR_AMX_S      3
#define SH7750_MCR_AMX_DRAM_8BIT_COL    0x00000000 /* 8-bit column addr */
#define SH7750_MCR_AMX_DRAM_9BIT_COL    0x00000008 /* 9-bit column addr */
#define SH7750_MCR_AMX_DRAM_10BIT_COL   0x00000010 /* 10-bit column addr */
#define SH7750_MCR_AMX_DRAM_11BIT_COL   0x00000018 /* 11-bit column addr */
#define SH7750_MCR_AMX_DRAM_12BIT_COL   0x00000020 /* 12-bit column addr */
/* See SH7750 Hardware Manual for SDRAM address multiplexor selection */

#define SH7750_MCR_RFSH       0x00000004 /* Refresh Control */
#define SH7750_MCR_RMODE      0x00000002 /* Refresh Mode: */
#define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */
#define SH7750_MCR_RMODE_SELF   0x00000002 /* Self-Refresh Mode */
#define SH7750_MCR_RMODE_EDO    0x00000001 /* EDO Mode */

/* SDRAM Mode Set address */
#define SH7750_SDRAM_MODE_A2_BASE  0xFF900000
#define SH7750_SDRAM_MODE_A3_BASE  0xFF940000
#define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2))
#define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2))
#define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3))
#define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3))


/* PCMCIA Control Register (half) - PCR */
#define SH7750_PCR_REGOFS     0x800018 /* offset */
#define SH7750_PCR            SH7750_P4_REG32(SH7750_PCR_REGOFS)
#define SH7750_PCR_A7         SH7750_A7_REG32(SH7750_PCR_REGOFS)

#define SH7750_PCR_A5PCW      0xC000 /* Area 5 PCMCIA Wait - Number of wait
                                        states to be added to the number of
                                        waits specified by WCR2 in a low-speed
                                        PCMCIA wait cycle */