sh7750_regs.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define SH7750_RDAYAR         SH7750_P4_REG32(SH7750_RDAYAR_REGOFS)
#define SH7750_RDAYAR_A7      SH7750_A7_REG32(SH7750_RDAYAR_REGOFS)
#define SH7750_RDAYAR_ENB     0x80    /* Day Alarm Enable */

/* Month Counter Register (byte, BCD-coded) - RMONAR */
#define SH7750_RMONAR_REGOFS  0xC80034  /* offset */
#define SH7750_RMONAR         SH7750_P4_REG32(SH7750_RMONAR_REGOFS)
#define SH7750_RMONAR_A7      SH7750_A7_REG32(SH7750_RMONAR_REGOFS)
#define SH7750_RMONAR_ENB     0x80    /* Month Alarm Enable */

/* RTC Control Register 1 (byte) - RCR1 */
#define SH7750_RCR1_REGOFS    0xC80038  /* offset */
#define SH7750_RCR1           SH7750_P4_REG32(SH7750_RCR1_REGOFS)
#define SH7750_RCR1_A7        SH7750_A7_REG32(SH7750_RCR1_REGOFS)
#define SH7750_RCR1_CF        0x80  /* Carry Flag */
#define SH7750_RCR1_CIE       0x10  /* Carry Interrupt Enable */
#define SH7750_RCR1_AIE       0x08  /* Alarm Interrupt Enable */
#define SH7750_RCR1_AF        0x01  /* Alarm Flag */

/* RTC Control Register 2 (byte) - RCR2 */
#define SH7750_RCR2_REGOFS    0xC8003C  /* offset */
#define SH7750_RCR2           SH7750_P4_REG32(SH7750_RCR2_REGOFS)
#define SH7750_RCR2_A7        SH7750_A7_REG32(SH7750_RCR2_REGOFS)
#define SH7750_RCR2_PEF        0x80  /* Periodic Interrupt Flag */
#define SH7750_RCR2_PES        0x70  /* Periodic Interrupt Enable: */
#define SH7750_RCR2_PES_DIS    0x00  /*   Periodic Interrupt Disabled */
#define SH7750_RCR2_PES_DIV256 0x10  /*   Generated at 1/256 sec interval */
#define SH7750_RCR2_PES_DIV64  0x20  /*   Generated at 1/64 sec interval */
#define SH7750_RCR2_PES_DIV16  0x30  /*   Generated at 1/16 sec interval */
#define SH7750_RCR2_PES_DIV4   0x40  /*   Generated at 1/4 sec interval */
#define SH7750_RCR2_PES_DIV2   0x50  /*   Generated at 1/2 sec interval */
#define SH7750_RCR2_PES_x1     0x60  /*   Generated at 1 sec interval */
#define SH7750_RCR2_PES_x2     0x70  /*   Generated at 2 sec interval */
#define SH7750_RCR2_RTCEN      0x08  /* RTC Crystal Oscillator is Operated */
#define SH7750_RCR2_ADJ        0x04  /* 30-Second Adjastment */
#define SH7750_RCR2_RESET      0x02  /* Frequency divider circuits are reset*/
#define SH7750_RCR2_START      0x01  /* 0 - sec, min, hr, day-of-week, month,
                                            year counters are stopped
                                        1 - sec, min, hr, day-of-week, month,
                                            year counters operate normally */


/*
 * Timer Unit (TMU)
 */
/* Timer Output Control Register (byte) - TOCR */
#define SH7750_TOCR_REGOFS    0xD80000  /* offset */
#define SH7750_TOCR           SH7750_P4_REG32(SH7750_TOCR_REGOFS)
#define SH7750_TOCR_A7        SH7750_A7_REG32(SH7750_TOCR_REGOFS)
#define SH7750_TOCR_TCOE      0x01  /* Timer Clock Pin Control:
                                          0 - TCLK is used as external clock
                                              input or input capture control
                                          1 - TCLK is used as on-chip RTC
                                              output clock pin */

/* Timer Start Register (byte) - TSTR */
#define SH7750_TSTR_REGOFS    0xD80004  /* offset */
#define SH7750_TSTR           SH7750_P4_REG32(SH7750_TSTR_REGOFS)
#define SH7750_TSTR_A7        SH7750_A7_REG32(SH7750_TSTR_REGOFS)
#define SH7750_TSTR_STR2      0x04  /* TCNT2 performs count operations */
#define SH7750_TSTR_STR1      0x02  /* TCNT1 performs count operations */
#define SH7750_TSTR_STR0      0x01  /* TCNT0 performs count operations */
#define SH7750_TSTR_STR(n)    (1 << (n))

/* Timer Constant Register - TCOR0, TCOR1, TCOR2 */
#define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12)) /* offset */
#define SH7750_TCOR(n)        SH7750_P4_REG32(SH7750_TCOR_REGOFS(n))
#define SH7750_TCOR_A7(n)     SH7750_A7_REG32(SH7750_TCOR_REGOFS(n))
#define SH7750_TCOR0          SH7750_TCOR(0)
#define SH7750_TCOR1          SH7750_TCOR(1)
#define SH7750_TCOR2          SH7750_TCOR(2)
#define SH7750_TCOR0_A7       SH7750_TCOR_A7(0)
#define SH7750_TCOR1_A7       SH7750_TCOR_A7(1)
#define SH7750_TCOR2_A7       SH7750_TCOR_A7(2)

/* Timer Counter Register - TCNT0, TCNT1, TCNT2 */
#define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12)) /* offset */
#define SH7750_TCNT(n)        SH7750_P4_REG32(SH7750_TCNT_REGOFS(n))
#define SH7750_TCNT_A7(n)     SH7750_A7_REG32(SH7750_TCNT_REGOFS(n))
#define SH7750_TCNT0          SH7750_TCNT(0)
#define SH7750_TCNT1          SH7750_TCNT(1)
#define SH7750_TCNT2          SH7750_TCNT(2)
#define SH7750_TCNT0_A7       SH7750_TCNT_A7(0)
#define SH7750_TCNT1_A7       SH7750_TCNT_A7(1)
#define SH7750_TCNT2_A7       SH7750_TCNT_A7(2)

/* Timer Control Register (half) - TCR0, TCR1, TCR2 */
#define SH7750_TCR_REGOFS(n)  (0xD80010 + ((n)*12)) /* offset */
#define SH7750_TCR(n)         SH7750_P4_REG32(SH7750_TCR_REGOFS(n))
#define SH7750_TCR_A7(n)      SH7750_A7_REG32(SH7750_TCR_REGOFS(n))
#define SH7750_TCR0           SH7750_TCR(0)
#define SH7750_TCR1           SH7750_TCR(1)
#define SH7750_TCR2           SH7750_TCR(2)
#define SH7750_TCR0_A7        SH7750_TCR_A7(0)
#define SH7750_TCR1_A7        SH7750_TCR_A7(1)
#define SH7750_TCR2_A7        SH7750_TCR_A7(2)

#define SH7750_TCR2_ICPF       0x200  /* Input Capture Interrupt Flag
                                        (1 - input capture has occured) */
#define SH7750_TCR_UNF         0x100  /* Underflow flag */
#define SH7750_TCR2_ICPE       0x0C0  /* Input Capture Control: */
#define SH7750_TCR2_ICPE_DIS   0x000  /*   Input Capture function is not used*/
#define SH7750_TCR2_ICPE_NOINT 0x080  /*   Input Capture function is used, but
                                           input capture interrupt is not
                                           enabled */
#define SH7750_TCR2_ICPE_INT   0x0C0  /*   Input Capture function is used,
                                           input capture interrupt enabled */
#define SH7750_TCR_UNIE        0x020  /* Underflow Interrupt Control
                                         (1 - underflow interrupt enabled) */
#define SH7750_TCR_CKEG        0x018  /* Clock Edge selection: */
#define SH7750_TCR_CKEG_RAISE  0x000  /*   Count/capture on rising edge */
#define SH7750_TCR_CKEG_FALL   0x008  /*   Count/capture on falling edge */
#define SH7750_TCR_CKEG_BOTH   0x018  /*   Count/capture on both rising and
                                           falling edges */
#define SH7750_TCR_TPSC         0x007  /* Timer prescaler */
#define SH7750_TCR_TPSC_DIV4    0x000  /*   Counts on peripheral clock/4 */
#define SH7750_TCR_TPSC_DIV16   0x001  /*   Counts on peripheral clock/16 */
#define SH7750_TCR_TPSC_DIV64   0x002  /*   Counts on peripheral clock/64 */
#define SH7750_TCR_TPSC_DIV256  0x003  /*   Counts on peripheral clock/256 */
#define SH7750_TCR_TPSC_DIV1024 0x004  /*   Counts on peripheral clock/1024 */
#define SH7750_TCR_TPSC_RTC     0x006  /*   Counts on on-chip RTC output clk*/
#define SH7750_TCR_TPSC_EXT     0x007  /*   Counts on external clock */

/* Input Capture Register (read-only) - TCPR2 */
#define SH7750_TCPR2_REGOFS   0xD8002C /* offset */
#define SH7750_TCPR2          SH7750_P4_REG32(SH7750_TCPR2_REGOFS)
#define SH7750_TCPR2_A7       SH7750_A7_REG32(SH7750_TCPR2_REGOFS)

/*
 * Bus State Controller - BSC
 */
/* Bus Control Register 1 - BCR1 */
#define SH7750_BCR1_REGOFS    0x800000 /* offset */
#define SH7750_BCR1           SH7750_P4_REG32(SH7750_BCR1_REGOFS)
#define SH7750_BCR1_A7        SH7750_A7_REG32(SH7750_BCR1_REGOFS)
#define SH7750_BCR1_ENDIAN    0x80000000 /* Endianness (1 - little endian) */
#define SH7750_BCR1_MASTER    0x40000000 /* Master/Slave mode (1-master) */
#define SH7750_BCR1_A0MPX     0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ 
#define SH7750_BCR1_IPUP      0x02000000 /* Input Pin Pull-up Control:
                                              0 - pull-up resistor is on for
                                                  control input pins
                                              1 - pull-up resistor is off */
#define SH7750_BCR1_OPUP      0x01000000 /* Output Pin Pull-up Control:
                                              0 - pull-up resistor is on for
                                                  control output pins
                                              1 - pull-up resistor is off */
#define SH7750_BCR1_A1MBC     0x00200000 /* Area 1 SRAM Byte Control Mode:
                                              0 - Area 1 SRAM is set to
                                                  normal mode
                                              1 - Area 1 SRAM is set to byte
                                                  control mode */
#define SH7750_BCR1_A4MBC     0x00100000 /* Area 4 SRAM Byte Control Mode:
                                              0 - Area 4 SRAM is set to
                                                  normal mode
                                              1 - Area 4 SRAM is set to byte
                                                  control mode */
#define SH7750_BCR1_BREQEN    0x00080000 /* BREQ Enable:
                                              0 - External requests are  not
                                                  accepted
                                              1 - External requests are 
                                                  accepted */
#define SH7750_BCR1_PSHR      0x00040000 /* Partial Sharing Bit:
                                              0 - Master Mode
                                              1 - Partial-sharing Mode */
#define SH7750_BCR1_MEMMPX    0x00020000 /* Area 1 to 6 MPX Interface:
                                              0 - SRAM/burst ROM interface
                                              1 - MPX interface */
#define SH7750_BCR1_HIZMEM    0x00008000 /* High Impendance Control. Specifies
                                            the state of A[25:0], BS\, CSn\,
                                            RD/WR\, CE2A\, CE2B\ in standby
                                            mode and when bus is released:
                                              0 - signals go to High-Z mode
                                              1 - signals driven */
#define SH7750_BCR1_HIZCNT    0x00004000 /* High Impendance Control. Specifies
                                            the state of the RAS\, RAS2\, WEn\,
                                            CASn\, DQMn, RD\, CASS\, FRAME\,
                                            RD2\ signals in standby mode and
                                            when bus is released:
                                              0 - signals go to High-Z mode
                                              1 - signals driven */
#define SH7750_BCR1_A0BST     0x00003800 /* Area 0 Burst ROM Control */
#define SH7750_BCR1_A0BST_SRAM    0x0000 /*   Area 0 accessed as SRAM i/f */
#define SH7750_BCR1_A0BST_ROM4    0x0800 /*   Area 0 accessed as burst ROM
                                              interface, 4 cosequtive access*/
#define SH7750_BCR1_A0BST_ROM8    0x1000 /*   Area 0 accessed as burst ROM
                                              interface, 8 cosequtive access*/
#define SH7750_BCR1_A0BST_ROM16   0x1800 /*   Area 0 accessed as burst ROM
                                              interface, 16 cosequtive access*/
#define SH7750_BCR1_A0BST_ROM32   0x2000 /*   Area 0 accessed as burst ROM
                                              interface, 32 cosequtive access*/

#define SH7750_BCR1_A5BST     0x00000700 /* Area 5 Burst ROM Control */
#define SH7750_BCR1_A5BST_SRAM    0x0000 /*   Area 5 accessed as SRAM i/f */
#define SH7750_BCR1_A5BST_ROM4    0x0100 /*   Area 5 accessed as burst ROM
                                              interface, 4 cosequtive access*/
#define SH7750_BCR1_A5BST_ROM8    0x0200 /*   Area 5 accessed as burst ROM
                                              interface, 8 cosequtive access*/
#define SH7750_BCR1_A5BST_ROM16   0x0300 /*   Area 5 accessed as burst ROM
                                              interface, 16 cosequtive access*/
#define SH7750_BCR1_A5BST_ROM32   0x0400 /*   Area 5 accessed as burst ROM
                                              interface, 32 cosequtive access*/

#define SH7750_BCR1_A6BST     0x000000E0 /* Area 6 Burst ROM Control */
#define SH7750_BCR1_A6BST_SRAM    0x0000 /*   Area 6 accessed as SRAM i/f */
#define SH7750_BCR1_A6BST_ROM4    0x0020 /*   Area 6 accessed as burst ROM
                                              interface, 4 cosequtive access*/
#define SH7750_BCR1_A6BST_ROM8    0x0040 /*   Area 6 accessed as burst ROM
                                              interface, 8 cosequtive access*/
#define SH7750_BCR1_A6BST_ROM16   0x0060 /*   Area 6 accessed as burst ROM
                                              interface, 16 cosequtive access*/
#define SH7750_BCR1_A6BST_ROM32   0x0080 /*   Area 6 accessed as burst ROM
                                              interface, 32 cosequtive access*/

#define SH7750_BCR1_DRAMTP        0x001C /* Area 2 and 3 Memory Type */
#define SH7750_BCR1_DRAMTP_2SRAM_3SRAM   0x0000 /* Area 2 and 3 are SRAM or MPX
                                                   interface. */
#define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM  0x0008 /* Area 2 - SRAM/MPX, Area 3 -
                                                   synchronous DRAM */
#define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are synchronous
                                                   DRAM interface */
#define SH7750_BCR1_DRAMTP_2SRAM_3DRAM   0x0010 /* Area 2 - SRAM/MPX, Area 3 -
                                                   DRAM interface */
#define SH7750_BCR1_DRAMTP_2DRAM_3DRAM   0x0014 /* Area 2 and 3 are DRAM
                                                   interface */

#define SH7750_BCR1_A56PCM    0x00000001 /* Area 5 and 6 Bus Type:
                                              0 - SRAM interface
                                              1 - PCMCIA interface */

/* Bus Control Register 2 (half) - BCR2 */
#define SH7750_BCR2_REGOFS    0x800004 /* offset */
#define SH7750_BCR2           SH7750_P4_REG32(SH7750_BCR2_REGOFS)
#define SH7750_BCR2_A7        SH7750_A7_REG32(SH7750_BCR2_REGOFS)

#define SH7750_BCR2_A0SZ      0xC000 /* Area 0 Bus Width */
#define SH7750_BCR2_A0SZ_S    14
#define SH7750_BCR2_A6SZ      0x3000 /* Area 6 Bus Width */
#define SH7750_BCR2_A6SZ_S    12
#define SH7750_BCR2_A5SZ      0x0C00 /* Area 5 Bus Width */
#define SH7750_BCR2_A5SZ_S    10
#define SH7750_BCR2_A4SZ      0x0300 /* Area 4 Bus Width */
#define SH7750_BCR2_A4SZ_S    8
#define SH7750_BCR2_A3SZ      0x00C0 /* Area 3 Bus Width */