sh7750_regs.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/* Peripheral Module Interrupts - Serial Communication Interface (SCI) */
#define SH7750_EVT_SCI_ERI             0x4E0 /* Receive Error */
#define SH7750_EVT_SCI_RXI             0x500 /* Receive Data Register Full */
#define SH7750_EVT_SCI_TXI             0x520 /* Transmit Data Register Empty */
#define SH7750_EVT_SCI_TEI             0x540 /* Transmit End */

/* Peripheral Module Interrupts - Watchdog Timer (WDT) */
#define SH7750_EVT_WDT_ITI             0x560 /* Interval Timer Interrupt
                                                (used when WDT operates in
                                                interval timer mode) */

/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
#define SH7750_EVT_REF_RCMI            0x580 /* Compare-match Interrupt */
#define SH7750_EVT_REF_ROVI            0x5A0 /* Refresh Counter Overflow 
                                                interrupt */

/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
#define SH7750_EVT_HUDI                0x600 /* UDI interrupt */

/* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */
#define SH7750_EVT_GPIO                0x620 /* GPIO Interrupt */

/* Peripheral Module Interrupts - DMA Controller (DMAC) */
#define SH7750_EVT_DMAC_DMTE0          0x640 /* DMAC 0 Transfer End Interrupt*/
#define SH7750_EVT_DMAC_DMTE1          0x660 /* DMAC 1 Transfer End Interrupt*/
#define SH7750_EVT_DMAC_DMTE2          0x680 /* DMAC 2 Transfer End Interrupt*/
#define SH7750_EVT_DMAC_DMTE3          0x6A0 /* DMAC 3 Transfer End Interrupt*/
#define SH7750_EVT_DMAC_DMAE           0x6C0 /* DMAC Address Error Interrupt */

/* Peripheral Module Interrupts - Serial Communication Interface with FIFO */
/*                                                                  (SCIF) */
#define SH7750_EVT_SCIF_ERI            0x700 /* Receive Error */
#define SH7750_EVT_SCIF_RXI            0x720 /* Receive FIFO Data Full or
                                                Receive Data ready interrupt */
#define SH7750_EVT_SCIF_BRI            0x740 /* Break or overrun error */
#define SH7750_EVT_SCIF_TXI            0x760 /* Transmit FIFO Data Empty */

/*
 * Power Management
 */
#define SH7750_STBCR_REGOFS   0xC00004  /* offset */
#define SH7750_STBCR          SH7750_P4_REG32(SH7750_STBCR_REGOFS)
#define SH7750_STBCR_A7       SH7750_A7_REG32(SH7750_STBCR_REGOFS)

#define SH7750_STBCR_STBY     0x80 /* Specifies a transition to standby mode:
                                      0 - Transition to SLEEP mode on SLEEP
                                      1 - Transition to STANDBY mode on SLEEP*/
#define SH7750_STBCR_PHZ      0x40 /* State of peripheral module pins in
                                      standby mode:
                                         0 - normal state
                                         1 - high-impendance state */
                                
#define SH7750_STBCR_PPU      0x20 /* Peripheral module pins pull-up controls*/
#define SH7750_STBCR_MSTP4    0x10 /* Stopping the clock supply to DMAC */
#define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
#define SH7750_STBCR_MSTP3    0x08 /* Stopping the clock supply to SCIF */
#define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3
#define SH7750_STBCR_MSTP2    0x04 /* Stopping the clock supply to TMU */
#define SH7750_STBCR_TMU_STP  SH7750_STBCR_MSTP2
#define SH7750_STBCR_MSTP1    0x02 /* Stopping the clock supply to RTC */
#define SH7750_STBCR_RTC_STP  SH7750_STBCR_MSTP1
#define SH7750_STBCR_MSPT0    0x01 /* Stopping the clock supply to SCI */
#define SH7750_STBCR_SCI_STP  SH7750_STBCR_MSTP0

#define SH7750_STBCR_STBY     0x80


#define SH7750_STBCR2_REGOFS  0xC00010  /* offset */
#define SH7750_STBCR2         SH7750_P4_REG32(SH7750_STBCR2_REGOFS)
#define SH7750_STBCR2_A7      SH7750_A7_REG32(SH7750_STBCR2_REGOFS)

#define SH7750_STBCR2_DSLP    0x80 /* Specifies transition to deep sleep mode:
                                      0 - transition to sleep or standby mode
                                          as it is specified in STBY bit
                                      1 - transition to deep sleep mode on
                                          execution of SLEEP instruction */
#define SH7750_STBCR2_MSTP6   0x02 /* Stopping the clock supply to Store Queue
                                      in the cache controller */
#define SH7750_STBCR2_SQ_STP  SH7750_STBCR2_MSTP6
#define SH7750_STBCR2_MSTP5   0x01 /* Stopping the clock supply to the User
                                      Break Controller (UBC) */
#define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5

/*
 * Clock Pulse Generator (CPG)
 */
#define SH7750_FRQCR_REGOFS   0xC00000  /* offset */
#define SH7750_FRQCR          SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
#define SH7750_FRQCR_A7       SH7750_A7_REG32(SH7750_FRQCR_REGOFS)

#define SH7750_FRQCR_CKOEN    0x0800 /* Clock Output Enable 
                                          0 - CKIO pin goes to HiZ/pullup
                                          1 - Clock is output from CKIO */
#define SH7750_FRQCR_PLL1EN   0x0400 /* PLL circuit 1 enable */
#define SH7750_FRQCR_PLL2EN   0x0200 /* PLL circuit 2 enable */

#define SH7750_FRQCR_IFC      0x01C0 /* CPU clock frequency division ratio: */
#define SH7750_FRQCR_IFCDIV1  0x0000 /*    0 - * 1 */
#define SH7750_FRQCR_IFCDIV2  0x0040 /*    1 - * 1/2 */
#define SH7750_FRQCR_IFCDIV3  0x0080 /*    2 - * 1/3 */
#define SH7750_FRQCR_IFCDIV4  0x00C0 /*    3 - * 1/4 */
#define SH7750_FRQCR_IFCDIV6  0x0100 /*    4 - * 1/6 */
#define SH7750_FRQCR_IFCDIV8  0x0140 /*    5 - * 1/8 */

#define SH7750_FRQCR_BFC      0x0038 /* Bus clock frequency division ratio: */
#define SH7750_FRQCR_BFCDIV1  0x0000 /*    0 - * 1 */
#define SH7750_FRQCR_BFCDIV2  0x0008 /*    1 - * 1/2 */
#define SH7750_FRQCR_BFCDIV3  0x0010 /*    2 - * 1/3 */
#define SH7750_FRQCR_BFCDIV4  0x0018 /*    3 - * 1/4 */
#define SH7750_FRQCR_BFCDIV6  0x0020 /*    4 - * 1/6 */
#define SH7750_FRQCR_BFCDIV8  0x0028 /*    5 - * 1/8 */

#define SH7750_FRQCR_PFC      0x0007 /* Peripheral module clock frequency
                                        division ratio: */
#define SH7750_FRQCR_PFCDIV2  0x0000 /*    0 - * 1/2 */
#define SH7750_FRQCR_PFCDIV3  0x0001 /*    1 - * 1/3 */
#define SH7750_FRQCR_PFCDIV4  0x0002 /*    2 - * 1/4 */
#define SH7750_FRQCR_PFCDIV6  0x0003 /*    3 - * 1/6 */
#define SH7750_FRQCR_PFCDIV8  0x0004 /*    4 - * 1/8 */

/*
 * Watchdog Timer (WDT)
 */
 
/* Watchdog Timer Counter register - WTCNT */
#define SH7750_WTCNT_REGOFS   0xC00008  /* offset */
#define SH7750_WTCNT          SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
#define SH7750_WTCNT_A7       SH7750_A7_REG32(SH7750_WTCNT_REGOFS)
#define SH7750_WTCNT_KEY      0x5A00  /* When WTCNT byte register written,
                                         you have to set the upper byte to
                                         0x5A */

/* Watchdog Timer Control/Status register - WTCSR */
#define SH7750_WTCSR_REGOFS   0xC0000C  /* offset */
#define SH7750_WTCSR          SH7750_P4_REG32(SH7750_WTCSR_REGOFS)
#define SH7750_WTCSR_A7       SH7750_A7_REG32(SH7750_WTCSR_REGOFS)
#define SH7750_WTCSR_KEY      0xA500  /* When WTCSR byte register written,
                                         you have to set the upper byte to
                                         0xA5 */
#define SH7750_WTCSR_TME      0x80  /* Timer enable (1-upcount start) */
#define SH7750_WTCSR_MODE     0x40  /* Timer Mode Select: */
#define SH7750_WTCSR_MODE_WT  0x40  /*    Watchdog Timer Mode */
#define SH7750_WTCSR_MODE_IT  0x00  /*    Interval Timer Mode */
#define SH7750_WTCSR_RSTS     0x20  /* Reset Select: */
#define SH7750_WTCSR_RST_MAN  0x20  /*    Manual Reset */
#define SH7750_WTCSR_RST_PWR  0x00  /*    Power-on Reset */
#define SH7750_WTCSR_WOVF     0x10  /* Watchdog Timer Overflow Flag */
#define SH7750_WTCSR_IOVF     0x08  /* Interval Timer Overflow Flag */
#define SH7750_WTCSR_CKS      0x07  /* Clock Select: */
#define SH7750_WTCSR_CKS_DIV32   0x00 /*   1/32 of frequency divider 2 input */
#define SH7750_WTCSR_CKS_DIV64   0x01 /*   1/64 */
#define SH7750_WTCSR_CKS_DIV128  0x02 /*   1/128 */
#define SH7750_WTCSR_CKS_DIV256  0x03 /*   1/256 */
#define SH7750_WTCSR_CKS_DIV512  0x04 /*   1/512 */
#define SH7750_WTCSR_CKS_DIV1024 0x05 /*   1/1024 */
#define SH7750_WTCSR_CKS_DIV2048 0x06 /*   1/2048 */
#define SH7750_WTCSR_CKS_DIV4096 0x07 /*   1/4096 */

/*
 * Real-Time Clock (RTC)
 */
/* 64-Hz Counter Register (byte, read-only) - R64CNT */
#define SH7750_R64CNT_REGOFS  0xC80000  /* offset */
#define SH7750_R64CNT         SH7750_P4_REG32(SH7750_R64CNT_REGOFS)
#define SH7750_R64CNT_A7      SH7750_A7_REG32(SH7750_R64CNT_REGOFS)

/* Second Counter Register (byte, BCD-coded) - RSECCNT */
#define SH7750_RSECCNT_REGOFS 0xC80004  /* offset */
#define SH7750_RSECCNT        SH7750_P4_REG32(SH7750_RSECCNT_REGOFS)
#define SH7750_RSECCNT_A7     SH7750_A7_REG32(SH7750_RSECCNT_REGOFS)

/* Minute Counter Register (byte, BCD-coded) - RMINCNT */
#define SH7750_RMINCNT_REGOFS 0xC80008  /* offset */
#define SH7750_RMINCNT        SH7750_P4_REG32(SH7750_RMINCNT_REGOFS)
#define SH7750_RMINCNT_A7     SH7750_A7_REG32(SH7750_RMINCNT_REGOFS)

/* Hour Counter Register (byte, BCD-coded) - RHRCNT */
#define SH7750_RHRCNT_REGOFS  0xC8000C  /* offset */
#define SH7750_RHRCNT         SH7750_P4_REG32(SH7750_RHRCNT_REGOFS)
#define SH7750_RHRCNT_A7      SH7750_A7_REG32(SH7750_RHRCNT_REGOFS)

/* Day-of-Week Counter Register (byte) - RWKCNT */
#define SH7750_RWKCNT_REGOFS  0xC80010  /* offset */
#define SH7750_RWKCNT         SH7750_P4_REG32(SH7750_RWKCNT_REGOFS)
#define SH7750_RWKCNT_A7      SH7750_A7_REG32(SH7750_RWKCNT_REGOFS)

#define SH7750_RWKCNT_SUN     0  /* Sunday */
#define SH7750_RWKCNT_MON     1  /* Monday */
#define SH7750_RWKCNT_TUE     2  /* Tuesday */
#define SH7750_RWKCNT_WED     3  /* Wednesday */
#define SH7750_RWKCNT_THU     4  /* Thursday */
#define SH7750_RWKCNT_FRI     5  /* Friday */
#define SH7750_RWKCNT_SAT     6  /* Saturday */

/* Day Counter Register (byte, BCD-coded) - RDAYCNT */
#define SH7750_RDAYCNT_REGOFS 0xC80014  /* offset */
#define SH7750_RDAYCNT        SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS)
#define SH7750_RDAYCNT_A7     SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS)

/* Month Counter Register (byte, BCD-coded) - RMONCNT */
#define SH7750_RMONCNT_REGOFS 0xC80018  /* offset */
#define SH7750_RMONCNT        SH7750_P4_REG32(SH7750_RMONCNT_REGOFS)
#define SH7750_RMONCNT_A7     SH7750_A7_REG32(SH7750_RMONCNT_REGOFS)

/* Year Counter Register (half, BCD-coded) - RYRCNT */
#define SH7750_RYRCNT_REGOFS  0xC8001C  /* offset */
#define SH7750_RYRCNT         SH7750_P4_REG32(SH7750_RYRCNT_REGOFS)
#define SH7750_RYRCNT_A7      SH7750_A7_REG32(SH7750_RYRCNT_REGOFS)

/* Second Alarm Register (byte, BCD-coded) - RSECAR */
#define SH7750_RSECAR_REGOFS  0xC80020  /* offset */
#define SH7750_RSECAR         SH7750_P4_REG32(SH7750_RSECAR_REGOFS)
#define SH7750_RSECAR_A7      SH7750_A7_REG32(SH7750_RSECAR_REGOFS)
#define SH7750_RSECAR_ENB     0x80    /* Second Alarm Enable */

/* Minute Alarm Register (byte, BCD-coded) - RMINAR */
#define SH7750_RMINAR_REGOFS  0xC80024  /* offset */
#define SH7750_RMINAR         SH7750_P4_REG32(SH7750_RMINAR_REGOFS)
#define SH7750_RMINAR_A7      SH7750_A7_REG32(SH7750_RMINAR_REGOFS)
#define SH7750_RMINAR_ENB     0x80    /* Minute Alarm Enable */

/* Hour Alarm Register (byte, BCD-coded) - RHRAR */
#define SH7750_RHRAR_REGOFS   0xC80028  /* offset */
#define SH7750_RHRAR          SH7750_P4_REG32(SH7750_RHRAR_REGOFS)
#define SH7750_RHRAR_A7       SH7750_A7_REG32(SH7750_RHRAR_REGOFS)
#define SH7750_RHRAR_ENB      0x80    /* Hour Alarm Enable */

/* Day-of-Week Alarm Register (byte) - RWKAR */
#define SH7750_RWKAR_REGOFS   0xC8002C  /* offset */
#define SH7750_RWKAR          SH7750_P4_REG32(SH7750_RWKAR_REGOFS)
#define SH7750_RWKAR_A7       SH7750_A7_REG32(SH7750_RWKAR_REGOFS)
#define SH7750_RWKAR_ENB      0x80    /* Day-of-week Alarm Enable */

#define SH7750_RWKAR_SUN      0  /* Sunday */
#define SH7750_RWKAR_MON      1  /* Monday */
#define SH7750_RWKAR_TUE      2  /* Tuesday */
#define SH7750_RWKAR_WED      3  /* Wednesday */
#define SH7750_RWKAR_THU      4  /* Thursday */
#define SH7750_RWKAR_FRI      5  /* Friday */
#define SH7750_RWKAR_SAT      6  /* Saturday */

/* Day Alarm Register (byte, BCD-coded) - RDAYAR */
#define SH7750_RDAYAR_REGOFS  0xC80030  /* offset */