start.s

来自「RTEMS (Real-Time Executive for Multiproc」· S 代码 · 共 804 行 · 第 1/2 页

		
	l.movhi	r7,hi(__ISR_Signals_to_thread_executing)
	l.ori	r7,r7,lo(__ISR_Signals_to_thread_executing)
	l.lwz	r12,0(r7)

	l.sfeqi	r8,0		# Skip if __Context... is false
	l.bf	L4_2
	l.movhi	r14,hi(__Thread_Dispatch)
	
	l.sfeqi	r12,0		# Skip if __ISR... is true
	l.bnf	L4_2
	l.ori	r14,r14,lo(__Thread_Dispatch)
	
	l.jalr	r14
	l.sw	0(r7),r0	# Set __ISR... to false
		
L4_2:			
	l.lwz	r9,0(r1)	#  Recover the return address
	l.jr	r9
	l.addi	r1,r1,8		#  Reset the stack
	
.endproc ___user_function
	.def	___user_function
	.val	.
	.scl	-1
	.endef

	
	/* Code wasted between here and 0x300 */
	
	/**************************************/
	/* Data Page Fault vector static code */
	/**************************************/
	.org	0x300
.proc	___data_page_fault
	.global	___data_page_fault
___data_page_fault:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,12(r11)
	l.j	___standard_exception
	l.addi	r3,r0,3
.endproc ___data_page_fault

	/* Code wasted between here and 0x400 */
		
	/*********************************************/
	/* Instruction Page Fault vector static code */
	/*********************************************/
	.org	0x400
.proc	___insn_page_fault
	.global	___insn_page_fault
___insn_page_fault:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,16(r11)
	l.j	___standard_exception
	l.addi	r3,r0,4
.endproc ___insn_page_fault

	/* Code wasted between here and 0x500 */
	
	/**************************************/
	/* Low Priority Interrupt static code */
	/**************************************/
	.org	0x500
.proc	___low_priority_int
	.global	___low_priority_int
___low_priority_int:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.mfspr	r3,r0,17			# Get the SR
	l.addi	r11,r0,-5			# r11 = 0xFFFFFFFB
	l.and	r11,r11,r3			# Clear the EIR bit
	l.mtspr	r0,r11,17			# Set the SR w/o INT
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,20(r11)
	l.j	___standard_exception
	l.addi	r3,r0,5
.endproc ___low_priority_int

	/* Code wasted between here and 0x600 */
	
	/******************************************/
	/* Alignment Exception vector static code */
	/******************************************/
	.org	0x600
.proc	___alignment_exception
	.global	___alignment_exception
___alignment_exception:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,24(r11)
	l.j	___standard_exception
	l.addi	r3,r0,6
.endproc ___alignment_exception

	/* Code wasted between here and 0x700 */
	
	/******************************************/
	/* Illegal Instruction vector static code */
	/******************************************/
	.org	0x700
.proc	___illegal_instruction
	.global	___illegal_instruction
___illegal_instruction:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,28(r11)
	l.j	___standard_exception
	l.addi	r3,r0,7
.endproc ___illegal_instruction

	/* Code wasted between here and 0x800 */
	
	/***************************************/
	/* High Priority Interrupt static code */
	/***************************************/
	.org	0x800
.proc	___high_priority_int
	.global	___high_priority_int
___high_priority_int:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.mfspr	r3,r0,17			# Get the SR
	l.addi	r11,r0,-5			# r11 = 0xFFFFFFFB
	l.and	r11,r11,r3			# Clear the EIR bit
	l.mtspr	r0,r11,17			# Set the SR w/o INT
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,32(r11)
	l.j	___standard_exception
	l.addi	r3,r0,8
.endproc ___high_priority_int

	/* Code wasted between here and 0x900 */
	
	/********************************/
	/* ITBL Miss vector static code */
	/********************************/
	.org	0x900
.proc	___ITBL_miss_exception
	.global	___ITBL_miss_exception
___ITBL_miss_exception:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,36(r11)
	l.j	___standard_exception
	l.addi	r3,r0,9
.endproc ___ITBL_miss_exception

	/* Code wasted between here and 0xA00 */
	
	/********************************/
	/* DTBL Miss vector static code */
	/********************************/
	.org	0xA00
.proc	___DTBL_miss_exception
	.global	___DTBL_miss_exception
___DTBL_miss_exception:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,40(r11)
	l.j	___standard_exception
	l.addi	r3,r0,10
.endproc ___DTBL_miss_exception

	/* Code wasted between here and 0xB00 */
	
	/**************************************/
	/* Range Exception vector static code */
	/**************************************/
	.org	0xB00
.proc	___range_exception
	.global	___range_exception
___range_exception:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,44(r11)
	l.j	___standard_exception
	l.addi	r3,r0,11
.endproc ___range_exception

	/* Code wasted between here and 0xC00 */
	
	/**********************************/
	/* System Call vector static code */
	/**********************************/
	.org	0xC00
.proc	___system_call
	.global	___system_call
___system_call:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,48(r11)
	l.j	___standard_exception
	l.addi	r3,r0,12
.endproc ___system_call

	/* Code wasted between here and 0xD00 */
	
	/**********************************/
	/* Breakpoint vector static code */
	/**********************************/
	.org	0xD00
.proc	___breakpoint
	.global	___breakpoint
___breakpoint:

	/* In keeping with the necessary requirements for
	   gdb to work, we are limiting this vector to
	   only 2 statements, which effect an immediate
	   return. At a later date, we may insert a debug
	   monitor here that will do even more, but for
	   now, this is all we want. */
	l.rfe
	l.nop

.endproc ___breakpoint

	/* Code wasted between here and 0xE00 */
	
	/*************************************/
	/* Trap Exception vector static code */
	/*************************************/
	.org	0xE00
.proc	___trap_exception
	.global	___trap_exception
___trap_exception:
	l.addi	r1,r1,-80
	l.sw	0(r1),r3
	l.sw	28(r1),r11
	l.movhi	r11,hi(_Or1k_Interrupt_Vectors)
	l.ori	r11,r11,lo(_Or1k_Interrupt_Vectors)
	l.lwz	r11,56(r11)
	l.j	___standard_exception
	l.addi	r3,r0,14
.endproc ___trap_exception

	/* Code wasted between here and 0x2000 */
	
	/* Exceptions from 0xF00 to 0x1F00 are not defined */
	/* in the Or1k architecture. They should be filled */
	/* in here for other implementations.              */

	.org	0x2000		/* Start after exception vector table */
		
	/*********************/
	/*       start       */
	/*********************/

	/* This is where we jump to right after the reset exception
	   handler. The system configuration information should
	   be passed to us in a pointer in r4. Generally, the
	   reset vector will call this routine directly, and
	   the memory configuration information will be stored
	   in the ROM/Flash image. It was decided no attempt
	   would be made to automatically determine this
	   information by probing, as the scheme would be too
	   complex and inherently unreliable. */

	/* Initialize strings and structures here */	
L_program:	
	.ascii	"RTEMS_or1k\000"
	.align	4
L_argv:	
	.word	L_program
				
.proc _start
	.def	_start
	.val	_start
	.scl	2
	.type	044
	.endef
	.global	_start
_start:	

	/* Initialize the memory controller here!
	   Discussions with Rudi have stated that
	   the first few bytes of the ROM image should 
	   contain a RAM map as opposed to trying to
	   figure out what to do based on probing. This
	   means a separate build of the OS for every
	   possible board configuration, but there
	   doesn't seem to be a better alternative. */

	/*** FIX ME! Initialize the external memory controller! ***/
	
	/* Move the data segment to RAM. Alternatively, we may
	   copy the text segment as well. For now, we'll assume
	   that the cache gives us sufficient performance that this
	   is not necessary. It will be very easy to add this later.
	 */	
	l.movhi		r4,hi(_etext)
	l.ori		r4,r4,lo(_etext)
	l.movhi		r5,hi(_BOTTOM_OF_MEMORY)
	l.ori		r5,r5,lo(_BOTTOM_OF_MEMORY)
	l.lwz		r5,0(r5)            # Dereference it
/*	l.add		r5,r5,r4	    # Place it in memory above the text segment*/
	l.movhi		r3,hi(_edata)
	l.ori		r3,r3,lo(_edata)
        l.movhi         r5,hi(_data_start)
        l.ori           r5,r5,lo(_data_start)
	
L3_0:	
	l.lwz		r6,0(r4)
	l.addi		r5,r5,4
	l.addi		r4,r4,4
	l.sfeq		r3,r5
	l.bnf		L3_0
	l.sw		-4(r5),r6           # Minimize write after read stalls

	/* Initialize the BSS segment */
	l.movhi		r3,hi(__end)
	l.ori		r3,r3,lo(__end)
/*	l.sub		r3,r3,r4
	l.add		r3,r3,r5*/
	l.sfleu		r3,r5
	l.bf		L3_2		   # Check for no BSS segment!
	l.nop
		
L3_1:
        l.addi          r5,r5,4
	l.sfeq		r5,r3
	l.bnf		L3_1
        l.sw            -4(r5),r0

L3_2:
	/* Tell everyone where the heap begins */
	l.movhi		r4,hi(__mem_end)
	l.ori		r4,r4,lo(__mem_end)
	l.sw		0(r4),r5
			
	/* Due to what I consider a bug in RTEMS, the entire
	   heap must be zeroed. I think this is the dumbest thing
	   I've ever heard, but whatever turns them on. I'd rather
	   see the code which depends on this behavior fixed. I
	   myself have never written code which assumes zeroes
	   will be returned from memory allocated from the heap. 
	   Anyway, if I don't do it here, I have to set a flag in
	   the CPU structure which then will do it anyway, but
	   from less efficient C code! Zero from here to the
	   stack pointer... One day when I'm old and gray maybe
	   I'll set this to random values instead and fix
	   whatever breaks. */
	
	l.sw		0(r5),r0
	l.sfeq		r5,r1
	l.bnf		L3_3
	l.addi		r5,r5,4	
	
L3_3:
	l.addi		r3,r0,1		/* Set argc to 1 */
	l.movhi		r4,hi(L_argv)	/* Initialize argv */
	l.ori		r4,r4,lo(L_argv)
	l.addi		r5,r5,0		/* Set envp to NULL */
		
        l.mfspr         r11,r0,17	/* Get SR value */
        l.ori           r11,r11,0x4     /* Set interrupt enable bit */
        l.jal           _boot_card      /* Boot up the card...run the OS */
        l.mtspr         r0,r11,17       /* Enable exceptions (DELAY) */
	
	/* We're done. We exited normally. Shut down. */
	l.jal		__exit
	l.nop
	
.endproc _start
	.def	_start
	.val	.
	.scl	-1
	.endef
	
	END_CODE