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## Description of SIS as related to this BSP## $Id: README,v 1.1.2.1 2005/10/05 19:25:45 joel Exp $#BSP NAME: sisBOARD: any based on the European Space Agency's ERC32BUS: N/ACPU FAMILY: sparcCPU: ERC32 (SPARC V7 + on-CPU peripherals) based on Cypress 601/602COPROCESSORS: on-chip 602 compatible FPUMODE: 32 bit modeDEBUG MONITOR: nonePERIPHERALS===========TIMERS: NAME: General Purpose Timer RESOLUTION: 50 nanoseconds - 12.8 microseconds NAME: Real Time Clock Timer RESOLUTION: 50 nanoseconds - 3.2768 milliseconds NAME: Watchdog Timer RESOLUTION: XXXSERIAL PORTS: 2 using on-chip UARTREAL-TIME CLOCK: noneDMA: on-chipVIDEO: noneSCSI: noneNETWORKING: noneDRIVER INFORMATION==================CLOCK DRIVER: ERC32 internal Real Time Clock TimerIOSUPP DRIVER: N/ASHMSUPP: N/ATIMER DRIVER: ERC32 internal General Purpose TimerCONSOLE DRIVER: ERC32 internal UART STDIO=====PORT: Channel AELECTRICAL: na since using simulatorBAUD: naBITS PER CHARACTER: naPARITY: naSTOP BITS: naNotes=====ERC32 BSP only supports single processor operations.A nice feature of this BSP is that the RAM and PROM size are set in the linkcmds file and the startup code programs the Memory ConfigurationRegister based on those sizes.The Watchdog Timer is disabled.This code was developed and tested entirely using the SPARC Instruction Simulator (SIS) for the ERC32. All tests were known to run correctlyagainst sis v1.7.Memory Map==========0x00000000 - 0x00000000 + _PROM_SIZE code and initialized data0x01f80000 on chip peripherals0x00000000 - 0x02000000 + _RAM_SIZE destination for initialized data BSS (i.e. unitialized data) C Heap (i.e. malloc area) RTEMS WorkspaceThe C heap is assigned all memory between the end of the BSS and the RTEMS Workspace. The size of the RTEMS Workspace is based on that specified in the application's configuration table.
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