erc32.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

                                               /* 0 = hold scalar and counter */
#define ERC32_MEC_TIMER_CONTROL_GSL    0x00000008  /* 1 = load scalar and start */
                                               /* 0 = no function */

#define ERC32_MEC_TIMER_CONTROL_RTCCR  0x00000100  /* 1 = reload at 0 */
                                               /* 0 = stop at 0 */
#define ERC32_MEC_TIMER_CONTROL_RTCCL  0x00000200  /* 1 = load and start */
                                               /* 0 = no function */
#define ERC32_MEC_TIMER_CONTROL_RTCSE  0x00000400  /* 1 = enable counting */
                                               /* 0 = hold scalar and counter */
#define ERC32_MEC_TIMER_CONTROL_RTCSL  0x00000800  /* 1 = load scalar and start */
                                               /* 0 = no function */

/*
 *  The following defines the bits in the UART Control Registers.
 *
 */

#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
 
/*
 *  The following defines the bits in the MEC UART Control Registers.
 */

#define ERC32_MEC_UART_STATUS_DR   0x00000001 /* Data Ready */
#define ERC32_MEC_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
#define ERC32_MEC_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
#define ERC32_MEC_UART_STATUS_FE   0x00000010 /* RX Framing Error */
#define ERC32_MEC_UART_STATUS_PE   0x00000020 /* RX Parity Error */
#define ERC32_MEC_UART_STATUS_OE   0x00000040 /* RX Overrun Error */
#define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
#define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */

#define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
#define ERC32_MEC_UART_STATUS_TSEA  (ERC32_MEC_UART_STATUS_TSE << 0)
#define ERC32_MEC_UART_STATUS_THEA  (ERC32_MEC_UART_STATUS_THE << 0)
#define ERC32_MEC_UART_STATUS_FEA   (ERC32_MEC_UART_STATUS_FE  << 0)
#define ERC32_MEC_UART_STATUS_PEA   (ERC32_MEC_UART_STATUS_PE  << 0)
#define ERC32_MEC_UART_STATUS_OEA   (ERC32_MEC_UART_STATUS_OE  << 0)
#define ERC32_MEC_UART_STATUS_CUA   (ERC32_MEC_UART_STATUS_CU  << 0)
#define ERC32_MEC_UART_STATUS_TXEA  (ERC32_MEC_UART_STATUS_TXE << 0)

#define ERC32_MEC_UART_STATUS_DRB   (ERC32_MEC_UART_STATUS_DR  << 16)
#define ERC32_MEC_UART_STATUS_TSEB  (ERC32_MEC_UART_STATUS_TSE << 16)
#define ERC32_MEC_UART_STATUS_THEB  (ERC32_MEC_UART_STATUS_THE << 16)
#define ERC32_MEC_UART_STATUS_FEB   (ERC32_MEC_UART_STATUS_FE  << 16)
#define ERC32_MEC_UART_STATUS_PEB   (ERC32_MEC_UART_STATUS_PE  << 16)
#define ERC32_MEC_UART_STATUS_OEB   (ERC32_MEC_UART_STATUS_OE  << 16)
#define ERC32_MEC_UART_STATUS_CUB   (ERC32_MEC_UART_STATUS_CU  << 16)
#define ERC32_MEC_UART_STATUS_TXEB  (ERC32_MEC_UART_STATUS_TXE << 16)

#ifndef ASM

/*
 *  This is used to manipulate the on-chip registers.
 *
 *  The following symbol must be defined in the linkcmds file and point
 *  to the correct location.
 */

extern ERC32_Register_Map ERC32_MEC;
 
/*
 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
 *  and the Interrupt Pending Registers.
 *
 *  NOTE: For operations which are not atomic, this code disables interrupts
 *        to guarantee there are no intervening accesses to the same register.
 *        The operations which read the register, modify the value and then
 *        store the result back are vulnerable.
 */

#define ERC32_Clear_interrupt( _source ) \
  do { \
    ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
  } while (0)

#define ERC32_Force_interrupt( _source ) \
  do { \
    unsigned32 _level; \
    \
    _level = sparc_disable_interrupts(); \
    ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
    ERC32_MEC.Interrupt_Force = (1 << (_source)); \
    sparc_enable_interrupts( _level ); \
  } while (0)
 
#define ERC32_Is_interrupt_pending( _source ) \
  (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
 
#define ERC32_Is_interrupt_masked( _source ) \
  (ERC32_MEC.Interrupt_Masked & (1 << (_source)))
 
#define ERC32_Mask_interrupt( _source ) \
  do { \
    unsigned32 _level; \
    \
    _level = sparc_disable_interrupts(); \
      ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
    sparc_enable_interrupts( _level ); \
  } while (0)
 
#define ERC32_Unmask_interrupt( _source ) \
  do { \
    unsigned32 _level; \
    \
    _level = sparc_disable_interrupts(); \
      ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
    sparc_enable_interrupts( _level ); \
  } while (0)

#define ERC32_Disable_interrupt( _source, _previous ) \
  do { \
    unsigned32 _level; \
    unsigned32 _mask = 1 << (_source); \
    \
    _level = sparc_disable_interrupts(); \
      (_previous) = ERC32_MEC.Interrupt_Mask; \
      ERC32_MEC.Interrupt_Mask = _previous | _mask; \
    sparc_enable_interrupts( _level ); \
    (_previous) &= _mask; \
  } while (0)
 
#define ERC32_Restore_interrupt( _source, _previous ) \
  do { \
    unsigned32 _level; \
    unsigned32 _mask = 1 << (_source); \
    \
    _level = sparc_disable_interrupts(); \
      ERC32_MEC.Interrupt_Mask = \
        (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
    sparc_enable_interrupts( _level ); \
  } while (0)

/*
 *  The following macros attempt to hide the fact that the General Purpose
 *  Timer and Real Time Clock Timer share the Timer Control Register.  Because
 *  the Timer Control Register is write only, we must mirror it in software
 *  and insure that writes to one timer do not alter the current settings
 *  and status of the other timer.
 *
 *  This code promotes the view that the two timers are completely independent.
 *  By exclusively using the routines below to access the Timer Control 
 *  Register, the application can view the system as having a General Purpose
 *  Timer Control Register and a Real Time Clock Timer Control Register 
 *  rather than the single shared value.
 *
 *  Each logical timer control register is organized as follows:
 *
 *    D0 - Counter Reload
 *          1 = reload counter at zero and restart
 *          0 = stop counter at zero
 *
 *    D1 - Counter Load
 *          1 = load counter with preset value and restart
 *          0 = no function
 *
 *    D2 - Enable
 *          1 = enable counting
 *          0 = hold scaler and counter
 *
 *    D3 - Scaler Load
 *          1 = load scalar with preset value and restart
 *          0 = no function
 *
 *  To insure the management of the mirror is atomic, we disable interrupts
 *  around updates.
 */

#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000001
#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO       0x00000000

#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER       0x00000002

#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING    0x00000004
#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING   0x00000000

#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER        0x00000008

#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK        0x00000001
#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK        0x00000004

#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK       0x0000000F
#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000005

extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;

/*
 *  This macros manipulate the General Purpose Timer portion of the 
 *  Timer Control register and promote the view that there are actually
 *  two independent Timer Control Registers.
 */

#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
  do { \
    unsigned32 _level; \
    unsigned32 _control; \
    unsigned32 __value; \
    \
    __value = ((_value) & 0x0f); \
    _level = sparc_disable_interrupts(); \
      _control = _ERC32_MEC_Timer_Control_Mirror; \
      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
      _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
      _control |= __value; \
      /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control );  */ \
      ERC32_MEC.Timer_Control = _control; \
    sparc_enable_interrupts( _level ); \
  } while ( 0 )

#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
  do { \
    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
  } while ( 0 )

/*
 *  This macros manipulate the Real Timer Clock Timer portion of the 
 *  Timer Control register and promote the view that there are actually
 *  two independent Timer Control Registers.
 */
 
#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
  do { \
    unsigned32 _level; \
    unsigned32 _control; \
    unsigned32 __value; \
    \
    __value = ((_value) & 0x0f) << 8; \
    _level = sparc_disable_interrupts(); \
      _control = _ERC32_MEC_Timer_Control_Mirror; \
      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
      _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
      _control |= __value; \
      /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
      ERC32_MEC.Timer_Control = _control; \
    sparc_enable_interrupts( _level ); \
  } while ( 0 )
 
#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
  do { \
    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
  } while ( 0 )


#endif /* !ASM */

#ifdef __cplusplus
}
#endif
 
#endif /* !_INCLUDE_ERC32_h */
/* end of include file */