bsp.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

    struct {
      unsigned short rtpr;          /* 0xFFF45024 - Receive Timeout Period */
    } w;
    struct {
      unsigned char rtprh;          /* 0xFFF45024 - Receive Timeout Period High */
      unsigned char rtprl;          /* 0xFFF45025 - Receive Timeout Period Low */
    } b;
  } u2;
  unsigned char     licr;           /* 0xFFF45026 - Local Interrupt Channel */
  unsigned char     reserved5[2];
  union {
    struct {
      unsigned char ttr;            /* 0xFFF45029 - Transmit Timer */
    } async;
    struct {
      unsigned char gt2;            /* 0xFFF45029 - General Timer 2 */
    } sync;
  } u3;
  union {
    struct {
      unsigned short gt1;           /* 0xFFF4502A - General Timer 1 */
    } w;
    struct {
      unsigned char gt1h;           /* 0xFFF4502A - General Timer 2 High */
      unsigned char gt1l;           /* 0xFFF4502B - General Timer 1 Low */
    } b;
  } u4;
  unsigned char     reserved6[2];
  unsigned char     lnxt;           /* 0xFF4502E - LNext Character */
  unsigned char     reserved7;
  unsigned char     rfoc;           /* 0xFFF45030 - Receive FIFO Output Count */
  unsigned char     reserved8[7];
  unsigned short    tcbadru;        /* 0xFF45038 - Transmit Current Buffer Address Upper */
  unsigned short    tcbadrl;        /* 0xFF4503A - Transmit Current Buffer Address Lower */
  unsigned short    rcbadru;        /* 0xFF4503C - Receive Current Buffer Address Upper */
  unsigned short    rcbadrl;        /* 0xFF4503E - Receive Current Buffer Address Lower */
  unsigned short    arbadru;        /* 0xFF45040 - A Receive Buffer Address Upper */
  unsigned short    arbardl;        /* 0xFF45042 - A Receive Buffer Address Lower */
  unsigned short    brbadru;        /* 0xFF45044 - B Receive Buffer Address Upper */
  unsigned short    brbadrl;        /* 0xFF45046 - B Receive Buffer Address Lower */
  unsigned short    brbcnt;         /* 0xFF45048 - B Receive Buffer Byte Count */
  unsigned short    arbcnt;         /* 0xFF4504A - A Receive Buffer Byte Count */
  unsigned short    reserved9;
  unsigned char     brbsts;         /* 0xFF4504E - B Receive Buffer Status */
  unsigned char     arbsts;         /* 0xFF4504F - A Receive Buffer Status */
  unsigned short    atbadru;        /* 0xFF45050 - A Transmit Buffer Address Upper */
  unsigned short    atbadrl;        /* 0xFF45052 - A Transmit Buffer Address Lower */
  unsigned short    btbadru;        /* 0xFF45054 - B Transmit Buffer Address Upper */
  unsigned short    btbadrl;        /* 0xFF45056 - B Transmit Buffer Address Lower */
  unsigned short    btbcnt;         /* 0xFF45058 - B Transmit Buffer Byte Count */
  unsigned short    atbcnt;         /* 0xFF4505A - A Transmit Buffer Byte Count */
  unsigned short    reserved10;
  unsigned char     btbsts;         /* 0xFF4505E - B Transmit Buffer Status */
  unsigned char     atbsts;         /* 0xFF4505F - A Transmit Buffer Status */
  unsigned char     reserved11[32];
  unsigned char     tftc;           /* 0xFFF45080 - Transmit FIFO Transfer Count */
  unsigned char     gfrcr;          /* 0xFFF45081 - Global Firmware Revision Code */
  unsigned char     reserved12[2];
  unsigned char     reoir;          /* 0xFFF45084 - Receive End Of Interrupt */
  unsigned char     teoir;          /* 0xFFF45085 - Transmit End Of Interrupt */
  unsigned char     meoir;          /* 0xFFF45086 - Modem End Of Interrupt */
  union {
    struct {
      unsigned short risr;          /* 0xFFF45088 - Receive Interrupt Status */
    } w;
    struct {
      unsigned char risrh;          /* 0xFFF45088 - Receive Interrupt Status High */
      unsigned char risrl;          /* 0xFFF45089 - Receive Interrupt Status Low */
    } b;
  } u5;   
  unsigned char     tisr;           /* 0xFFF4508A - Transmit Interrupt Status */
  unsigned char     misr;           /* 0xFFF4508B - Modem/Timer Interrupt Status */
  unsigned char     reserved13[2];
  unsigned char     bercnt;         /* 0xFFF4508E - Bus Error Retry Count */
  unsigned char     reserved14[49];
  unsigned char     tcor;           /* 0xFFF450C0 - Transmit Clock Option */
  unsigned char     reserved15[2];
  unsigned char     tbpr;           /* 0xFFF450C3 - Transmit Baud Rate Period */
  unsigned char     reserved16[4];
  unsigned char     rcor;           /* 0xFFF450C8 - Receive Clock Option */
  unsigned char     reserved17[2];
  unsigned char     rbpr;           /* 0xFFF450CB - Receive Baud Rate Period */
  unsigned char     reserved18[10];
  unsigned char     cpsr;           /* 0xFFF450D6 - CRC Polynomial Select */
  unsigned char     reserved19[3];
  unsigned char     tpr;            /* 0xFFF450DA - Timer Period */
  unsigned char     reserved20[3];
  unsigned char     msvr_rts;       /* 0xFFF450DE - Modem Signal Value - RTS */
  unsigned char     msvr_dtr;       /* 0xFFF450DF - Modem Signal Value - DTR */
  unsigned char     tpilr;          /* 0xFFF450E0 - Transmit Priority Interrupt Level */
  unsigned char     rpilr;          /* 0xFFF450E1 - Receive Priority Interrupt Level */
  unsigned char     stk;            /* 0xFFF450E2 - Stack */
  unsigned char     mpilr;          /* 0xFFF450E3 - Modem Priority Interrupt Level */
  unsigned char     reserved21[8];
  unsigned char     tir;            /* 0xFFF450EC - Transmit Interrupt */
  unsigned char     rir;            /* 0xFFF450ED - Receive Interrupt */
  unsigned char     car;            /* 0xFFF450EE - Channel Access */
  unsigned char     mir;            /* 0xFFF450EF - Model Interrupt */
  unsigned char     reserved22[6];
  unsigned char     dmr;            /* 0xFFF450F6 - DMA Mode */
  unsigned char     reserved23;
  unsigned char     dr;             /* 0xFFF450F8 - Receive/Transmit Data */
} cd2401_regs;


/*
 *  Base address of the CD2401.
 *  This is not configurable in the MVME167.
 */
#define cd2401          ((cd2401_regs * const) 0xFFF45000)


/* CD2401 is clocked at 20 MHz */
#define CD2401_CLK_RATE 20000000

/* BSP-wide functions */

void bsp_cleanup( void );

m68k_isr_entry set_vector(
  rtems_isr_entry     handler,
  rtems_vector_number vector,
  int                 type
);

#ifdef M167_INIT
#undef EXTERN
#define EXTERN
#else
#undef EXTERN
#define EXTERN extern
#endif

/*
 *  Device Driver Table Entries
 */

/*
 * NOTE: Use the standard Console driver entry
 */
 
/*
 * NOTE: Use the standard Clock driver entry
 */

/*
 * How many libio files we want
 */

#define BSP_LIBIO_MAX_FDS       20


/* miscellaneous stuff assumed to exist */

extern rtems_configuration_table BSP_Configuration;

extern m68k_isr_entry M68Kvec[];   /* vector table address */


/*
 *  Define the time limits for RTEMS Test Suite test durations.
 *  Long test and short test duration limits are provided.  These
 *  values are in seconds and need to be converted to ticks for the
 *  application.
 *
 */

#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */

/*
 *  Define the interrupt mechanism for Time Test 27 
 *
 *  NOTE: We use software interrupt 0
 */
#define MUST_WAIT_FOR_INTERRUPT 0

#define Install_tm27_vector( handler ) \
            set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
            lcsr->intr_level[2] |= 3; \
            lcsr->intr_ena |= 0x100

#define Cause_tm27_intr()  lcsr->intr_soft_set |= 0x100

#define Clear_tm27_intr()  lcsr->intr_clear |= 0x100

#define Lower_tm27_intr()

#ifdef __cplusplus
}
#endif

#endif
/* end of include file */