bsp.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*  bsp.h
 *
 *  Following defines must reflect the setup of the particular MVME167.
 *  All page references are to the MVME166/MVME167/MVME187 Single Board
 *  Computer Programmer's Reference Guide (MVME187PG/D2) with the April
 *  1993 supplements/addenda (MVME187PG/D2A1).
 *
 *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
 *  Modifications of respective RTEMS file:
 *  Copyright (c) 1998, National Research Council of Canada
 *
 *  $Id: bsp.h,v 1.10.4.1 2003/09/04 18:44:42 joel Exp $
 */

#ifndef __MVME167_H
#define __MVME167_H


#ifdef __cplusplus
extern "C" {
#endif

#include <bspopts.h>

#include <rtems.h>
#include <clockdrv.h>
#include <console.h>
#include <iosupp.h>
#include <rtems/bspIo.h>


/*
 *  confdefs.h overrides for this BSP:
 *   - termios serial ports (defaults to 1)
 *   - Interrupt stack space is not minimum if defined.
 */

#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 4
#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
  
#include <mvme16x_hw.h>

/* GCSR is in mvme16x_hw.h */
/* LCSR is in mvme16x_hw.h */
/* i82596 is in mvme16x_hw.h */
/* NVRAM is in mvme16x_hw.h */

#if 0
/*
 *  Representation of the PCCchip2
 */
typedef volatile struct pccchip2_regs_ {
  unsigned char     chip_id;            /* 0xFFF42000 */
  unsigned char     chip_revision;      /* 0xFFF42001 */
  unsigned char     gen_control;        /* 0xFFF42002 */
  unsigned char     vector_base;        /* 0xFFF42003 */
  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
  unsigned char     gpio_ctl;           /* 0xFFF42019 */
  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
  unsigned char     SCC_error;          /* 0xFFF4201C */
  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
  unsigned char     reserved1[3];
  unsigned char     modem_piack;        /* 0xFFF42023 */
  unsigned char     reserved2;
  unsigned char     tx_piack;           /* 0xFFF42025 */
  unsigned char     reserved3;
  unsigned char     rx_piack;           /* 0xFFF42027 */
  unsigned char     LANC_error;         /* 0xFFF42028 */
  unsigned char     reserved4;
  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
  unsigned char     SCSI_error;         /* 0xFFF4202C */
  unsigned char     reserved5[2];
  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
  unsigned char     reserved6;
  unsigned char     print_input_status; /* 0xFFF42036 */
  unsigned char     print_ctl;          /* 0xFFF42037 */
  unsigned char     chip_speed;         /* 0xFFF42038 */
  unsigned char     reserved7;
  unsigned char     print_data;         /* 0xFFF4203A */
  unsigned char     reserved8[3];
  unsigned char     int_level;          /* 0xFFF4203E */
  unsigned char     int_mask;           /* 0xFFF4203F */
} pccchip2_regs;

/*
 *  Base address of the PCCchip2.
 *  This is not configurable in the MVME167.
 */
#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)

#endif
/*
 * The MVME167 is equiped with one or two MEMC040 memory controllers at
 * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
 * were initialized by 167Bug.
 */
typedef volatile struct memc040_regs_ {
  unsigned char     chip_id;            /* 0xFFF43000/0xFFF43100 */
  unsigned char     reserved1[3];
  unsigned char     chip_revision;      /* 0xFFF43004/0xFFF43104 */
  unsigned char     reserved2[3];
  unsigned char     mem_config;         /* 0xFFF43008/0xFFF43108 */
  unsigned char     reserved3[3];
  unsigned char     alt_status;         /* 0xFFF4300C/0xFFF4310C */
  unsigned char     reserved4[3];
  unsigned char     alt_ctl;            /* 0xFFF43010/0xFFF43110 */
  unsigned char     reserved5[3];
  unsigned char     base_addr;          /* 0xFFF43014/0xFFF43114 */
  unsigned char     reserved6[3];
  unsigned char     ram_ctl;            /* 0xFFF43018/0xFFF43118 */
  unsigned char     reserved7[3];
  unsigned char     bus_clk;            /* 0xFFF4301C/0xFFF4311C */
} memc040_regs;

/*
 *  Base address of the MEMC040s.
 *  This is not configurable in the MVME167.
 */
#define memc040_1   ((memc040_regs * const) 0xFFF43000)
#define memc040_2   ((memc040_regs * const) 0xFFF43100)


/*
 *  The MVME167 may be equiped with error-correcting RAM cards. In this case,
 *  each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
 *  assumes that these controllers, if present, are initialized by 167Bug.
 *  They do not appear to hold information of interest at this time, so they
 *  are not described. However, each MCECC pair lives at the same address as
 *  the MEMC040 is replaces. The first eight registers of the MCECC are
 *  nearly identical to the ones of the MEMC040, and the memc040_X structures
 *  can be used to read those first eight registers.
 */
 

/*
 *  Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
 */
typedef volatile struct cd2401_regs_ {
  unsigned char     reserved1[7];
  unsigned char     cor7;           /* 0xFFF45007 - Channel Option 7 */
  unsigned char     reserved2;
  unsigned char     livr;           /* 0xFFF45009 - Local Interrupt Vector */
  unsigned char     reserved3[6];
  unsigned char     cor1;           /* 0xFFF45010 - Channel Option 1 */
  unsigned char     ier;            /* 0xFFF45011 - Interrupt Enable */
  unsigned char     stcr;           /* 0xFFF45012 - Special Transmit Command */
  unsigned char     ccr;            /* 0xFFF45013 - Channel Command */
  unsigned char     cor5;           /* 0xFFF45014 - Channel Option 5 */
  unsigned char     cor4;           /* 0xFFF45015 - Channel Option 4 */
  unsigned char     cor3;           /* 0xFFF45016 - Channel Option 3 */
  unsigned char     cor2;           /* 0xFFF45017 - Channel Option 2 */
  unsigned char     cor6;           /* 0xFFF45018 - Channel Option 6 */
  unsigned char     dmabsts;        /* 0xFFF45019 - DMA Buffer Status */
  unsigned char     csr;            /* 0xFFF4501A - Channel Status */
  unsigned char     cmr;            /* 0xFFF4501B - Channel Mode */
  union {
    struct {
      unsigned char schr4;          /* 0xFFF4501C - Special Character 4 */
      unsigned char schr3;          /* 0xFFF4501D - Special Character 3 */
      unsigned char schr2;          /* 0xFFF4501E - Special Character 2 */
      unsigned char schr1;          /* 0xFFF4501F - Special Character 1 */
    } async;
    struct {
      unsigned char rfar4;          /* 0xFFF4501C - Receive Frame Address 4 */
      unsigned char rfar3;          /* 0xFFF4501D - Receive Frame Address 3 */
      unsigned char rfar2;          /* 0xFFF4501E - Receive Frame Address 2 */
      unsigned char rfar1;          /* 0xFFF4501F - Receive Frame Address 1 */
    } sync;
  } u1;    
  unsigned char     reserved4[2];
  unsigned char     scrh;           /* 0xFFF45022 - Special Character Range High */
  unsigned char     scrl;           /* 0xFFF45023 - Special Character Range Low */
  union {