start.s

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

_crt0_warm_start:
	moveq.l #1,crt0_boot_type		 	| signal warm reset

_crt0_common_start:
	move.w	#0x2700,sr               		| disable interrupts and switch to interrupt mode
	movea.l	#_crt0_init_stktop,sp			| set up initialization stack

	move.l	#Entry,crt0_temp			| VBR initialization
	movec.l crt0_temp,vbr				|
	moveq.l #0x07,crt0_temp
	movec.l crt0_temp,dfc				| prepare access in CPU space
	move.l  #(BASE_SIM+0x111),crt0_temp 		| mask CPU, RESERVED USER SPACES
	moves.l crt0_temp,BASE_REG			| base initialization (must be MOVES, PCC-130795)

	movea.l #BASE_SIM,crt0_sim_base

	/* -- disable Bus Monitor -- */
	move.b  #0,SIM_SYPCR(crt0_sim_base)   		| system protection control register

	/* -- enable A31-A24 -- */
	clr.b   SIM_PPRA1(crt0_sim_base)

	/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
	move.w  #0x427F,SIM_MCR(crt0_sim_base)

	/* -- enable /IRQ3, 5, 6, 7 -- */
	move.b   #0xE8,SIM_PPRB(crt0_sim_base)

	/* -- enable autovector on /IRQ7 -- */
	move.b   #0x80,SIM_AVR(crt0_sim_base)

	/* -- test CPU type -- */
	cmp.b	  #_CPU349,SIM_IDR(crt0_sim_base)
	bne	  cpu_is_68340

/*-------------------------------------------------------------------------------------------*/
cpu_is_68349:

 	/* -- set cpu clock -- */
	move.w  #_SPEED349,SIM_SYNCR(crt0_sim_base)    		| clock

sync_wait349:
	btst.b	#3,(SIM_SYNCR+1)(crt0_sim_base)
	beq	sync_wait349

	/* to allow access to the EPLD internal registers, it is necessary
	to disable the global chip-select /CS0 (which decodes every external
	cycles). To do that, we initialize the 68349 internal RAM,
	copy a part of the initialization code in it, and jump there.
	from that moment, /CS0 is not used, therefore it can be initialized
	with its default value. Its width may be incorrect, but it will be
	adjusted later. The goal is to avoid any conflict with
	the accesses to the EPLD registers.
	When this is done, we read the RESET parameters (boot prom width
	and chip-select switch) and proceed with the initialization
	when all is done, we jump back to the boot prom now
	decoded with a properly configured /CS0 */

	/*-------------------------------------*/
	/* -- configure internal SRAM banks -- */

	move.l	#0x00000000,QDMM_MCR(crt0_sim_base)
	move.l	#_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
	move.l	#_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
	move.l	#_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
	move.l	#_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)

	/*--------------------------------------------------------*/
	/* -- copy to address of the 68349 initialization code -- */

	lea.l		_copy_start_code(%pc),crt0_ptr3
	lea.l		_copy_end_code(%pc),crt0_ptr4
	move.l		crt0_ptr4,crt0_temp
	sub.l		crt0_ptr3,crt0_temp
	add.l		#3,crt0_temp				| adjust to next long word
	lsr.l		#2,crt0_temp

	move.l		#_FastRam_Start,crt0_ptr4
_copy_loop:
	move.l		(crt0_ptr3)+,(crt0_ptr4)+
	subq.l		#1,crt0_temp
	bne.s		_copy_loop
	bra.l		_FastRam_Start				| jump to code in internal RAM

	/*------------------------------------*/
	/* -- start of initialization code -- */

_copy_start_code:
	bra.l		_begin_68349_init

	/*----------------------------------------------------------*/
	/*  Astecc  68349 board : chip-select initialization values */

_table_csepld:
	dc.b	(_EPLD_CS_BASE&0x0F)+0x80			| 16 bits, 0ws
	dc.b	0x80						| 16 bits, 0 ws
	dc.b	0x90						| 16 bits, ext /dsack
	dc.b	0x90						| 16 bits, ext /dsack

_table_cs349:
	dc.l	0x003FFFF4               			| Mask CS0 (4Mbytes PROM, 32bits, 1WS)
	dc.l	(_PROM_Start&0xFFFFFF00)+0x00000003  		| Base CS0
	dc.l    0x003FFFF1               			| MASK CS1 (4Mbytes RAM, 16bits, 0WS)
	dc.l	(_BCCram_Start&0xFFFFFF00)+0x00000003  		| Base CS1
	dc.l    0x000000FF               			| MASK CS2 (FLEX, ext DTACK, 256 bytes)
	dc.l	(_FLEX_Start&0xFFFFFF00)+0x00000003  		| Base CS2
	dc.l	0x000000FF               			| Mask CS3 (I2C, ext DTACK, 256 bytes)
	dc.l	(_I2C_Start&0xFFFFFF00)+0x00000003  		| Base CS3

	/*-------------------------------------------------*/
_begin_68349_init:

	/*-------------------------------------------------*/
	/* 68349 chip select initialization
	
	at this stage, the width of /CS0 may be incorrect
	it will be corrected later
	*/

_cs68349_init:
	lea.l   	SIM_MASKH0(crt0_sim_base),crt0_ptr4
	lea.l   	_table_cs349(%pc),crt0_ptr3

	moveq.l 	#0x07,crt0_temp
_cs349_init2:
	move.l  	(crt0_ptr3)+,(crt0_ptr4)+
	dbra    	crt0_temp,_cs349_init2

	/*-----------------------------------------------*/
	/* -- prepare access to the internal registers --*/
	moveq.l 	#EPLD_SPACE,crt0_temp
	movec.l 	crt0_temp,dfc
	movec.l 	crt0_temp,sfc
	move.l 		#GLUE_EPLD,crt0_glue
	move.l 		#DRAM_EPLD,crt0_dram

	/*-------------------------------------------*/
	/* EPLD generated /CS[3..0] must be disabled */

_csepld_clear:
	move.l		crt0_glue,crt0_ptr4
	move.w		#3,crt0_spare6
	clr.b		crt0_temp

_csepld_clear1:
	moves.b		crt0_temp,(crt0_ptr4)+
	dbra    	crt0_spare6,_csepld_clear1

	/*---------------------------------------------------------*/
	/* -- get width of boot PROM, and active chip-select set --*/
	moves.b  	REG_BUSWIDTH(crt0_dram),crt0_csswitch
	move.b		crt0_csswitch,crt0_buswidth

	/* state of CS_SWITCH  : sel == 0 => CPU chip_selects  (/CS[3..0])
	                       : sel == 1 => EPLD chip_selects (/CS[3..0]) */
	and.b		#1,crt0_csswitch

	/* bus width of /CS0 during reset		bw[1..0]  : 0   1   2       3
	                                   		bus width : 32  16  8   ext./dsackx */
	rol.b		#2,crt0_buswidth
	and.b		#3,crt0_buswidth

	/*----------------------------------------------------*/
	/* -- configure chip select 0 with boot prom width -- */
	lea.l   	SIM_MASKH0(crt0_sim_base),crt0_ptr4
	lea.l   	_table_cs349(%pc),crt0_ptr3
	move.l  	(crt0_ptr3)+,crt0_temp
	and.b		#0xFC,crt0_temp				| clear PS0 & PS1
	or.b		crt0_buswidth,crt0_temp			| set boot PROM bus width
	move.l		crt0_temp,(crt0_ptr4)+

	/*------------------------*/
	/* -- read PDCS buffer -- */
	moves.b		REG_PDCS(crt0_glue),crt0_pdcs
/*	move.b		#0x3F,crt0_pdcs 					pour test */


	/*---------------------------------------*/
	/* -- EPLD chip-select initialization -- */
	/*---------------------------------------*/
	btst.b		#0,crt0_csswitch
	beq		_cs_init_end

	/*--------------------------------------------*/
	/* 68349 generated /CS[3..0] must be disabled */
	lea.l   	SIM_MASKH0(crt0_sim_base),crt0_ptr4
	lea.l   	_table_cs349(%pc),crt0_ptr3
	moveq.l 	#0x03,crt0_temp
_cs349_clear:
	move.l  	(crt0_ptr3)+,(crt0_ptr4)+
	move.l  	(crt0_ptr3)+,crt0_spare6
	and.b		#0xFE,crt0_spare6			| disable chip-select
	move.l		crt0_spare6,(crt0_ptr4)+
	dbra    	crt0_temp,_cs349_clear

	/*---------------------------------------------*/
	/* EPLD generated /CS[3..0] must be configured */
_csepld_init:
	move.l		crt0_glue,crt0_ptr4
	lea.l   	_table_csepld(%pc),crt0_ptr3

	move.b  	(crt0_ptr3)+,crt0_temp
	or.b		#0x20,crt0_temp				| default width is 32 bits
	tst.b		crt0_buswidth				| is boot PROM bus width 32 bits ?
	beq		_csepld1				| if not
	and.b		#0xDF,crt0_temp				| set width to 16 bits
_csepld1:
	moves.b		crt0_temp,(crt0_ptr4)+

	moveq.l 	#0x02,crt0_spare6
_csepld2:
	move.b  	(crt0_ptr3)+,crt0_temp
	moves.b		crt0_temp,(crt0_ptr4)+
	dbra    	crt0_spare6,_csepld2

_cs_init_end:

	/*--------------------------------------*/
	/* -- DRAM controller initialization -- */
_dram_init:
	move.w 		#15,crt0_temp
	move.l		#_ExtRam_Start,crt0_ptr3

_dram_init1:
	clr.l		(crt0_ptr3)+				| must access DRAM
	dbra		crt0_temp,_dram_init1			| prior to init refresh

_dram_init2:
	move.b 		#3,crt0_temp
	moves.b		crt0_temp,REG_WS(crt0_dram) 		| set 3 wait-states

	move.b 		#0x81,crt0_temp
	moves.b		crt0_temp,REG_REFRESH(crt0_dram) 	| refresh every 10祍

	move.b 		#0,crt0_temp
	moves.b		crt0_temp,REG_CONFIG(crt0_dram)		| default size = 4Mbytes

	/*-----------------------*/
	/* -- configure cache -- */
_init_cache:
	move.l		#0x000001E0,CACHE_MCR(crt0_sim_base)
	btst.b		#bit_cache,crt0_pdcs
	bne		_init_cache_end
	or.l		#0x00000001,CACHE_MCR(crt0_sim_base)

_init_cache_end:

	/*-----------------------------*/
	/* -- timers initialization -- */

	clr.b 		crt0_temp
	moves.b		crt0_temp,REG_TIMER1(crt0_glue)		| disable timer 1
	moves.b		crt0_temp,REG_TIMER2(crt0_glue)		| disable timer 2

	/*--------------------------*/
	/* -- I2C initialization -- */
	move.b 		#3,crt0_temp
	moves.b		crt0_temp,REG_I2C(crt0_glue)		| tri-states I2C ports

	/*-----------------------------------------*/
	/* -- baudrate generator initialization -- */
	move.b 		#2,crt0_temp
	moves.b		crt0_temp,REG_BAUDRATE(crt0_glue) 	| baudrate = 38400

	/*-------------------------------*/
	/* --  IO port initialization -- */
	clr.b 		crt0_temp
	moves.b		crt0_temp,REG_IO(crt0_glue)		| set port as input

	/* -- */

	move.l 		#68349,crt0_cpu_type


	/* -- jump back to PROM -- */

	jmp.l		(_fill_test)				| must be absolute long

_copy_end_code:

/*-------------------------------------------------
  initialization code for the 68340 board
  -------------------------------------------------*/

	/* Astecc  68340 board : chip-select initialization values */
_table_cs340:
	dc.l	0x003FFFF0               		/* Mask CS0 (4Mbytes PROM, 32bits, 0WS)	*/
	dc.l	((_PROM_Start&0xFFFFFF00)+0x00000003)  	/* Base CS0 */
	dc.l    0x0000FFFD               		/* MASK CS1 (RAMBCC340, 0WS, FTE) */
	dc.l	((_BCCram_Start&0xFFFFFF00)+0x00000003)	/* Base CS1 */
	dc.l    0x000000FF               		/* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
	dc.l	((_FLEX_Start&0xFFFFFF00)+0x00000003)  	/* Base CS2 */
	dc.l	0x000000FF               		/* Mask CS3 (I2C, ext DTACK, 256 bytes)	*/
	dc.l	((_I2C_Start&0xFFFFFF00)+0x00000003)  	/* Base CS3 */

cpu_is_68340:

	/* -- set cpu clock -- */
	move.w  #_SPEED340,SIM_SYNCR(crt0_sim_base) 		| clock
sync_wait340:
	btst.b	#3,(SIM_SYNCR+1)(crt0_sim_base)
	beq	sync_wait340

	/* -- chip select initialization -- */
	lea.l   SIM_MASKH0(crt0_sim_base),crt0_ptr4
	lea.l   _table_cs340(%pc),crt0_ptr3
	moveq.l #0x07,crt0_temp
_b_cs340:
	move.l  (crt0_ptr3)+,crt0_ptr5
	move.l 	crt0_ptr5,(crt0_ptr4)+				| pour test
	dbra    crt0_temp,_b_cs340

	move.l	#68340,crt0_cpu_type
	move.b	#0,crt0_csswitch				| CPU
	move.b	#1,crt0_buswidth				| 16 bits


	/*-------------------------------------------------
	  fill RAM if COLDSTART
	  -------------------------------------------------*/
_fill_test:

  	tst.l 	crt0_boot_type
  	bne 	_dont_fill

	cmp.b	#_CPU349,SIM_IDR(crt0_sim_base)
	bne	_fill
	btst.b	#bit_meminit,crt0_pdcs
	bne	_dont_fill

	/* fill main memory */
_fill:
	move.l  #_crt0_init_stack,crt0_ptr3			| skip Astecc vars
  	move.l	#_ExtRam_Start,crt0_temp
	sub.l  	#_crt0_init_stack,crt0_temp
	add.l   #_ExtRam_Size,crt0_temp 			| get size
	lsr.l   #2,crt0_temp            			| ajust for long word
_fill_loop:
	clr.l 	(crt0_ptr3)+
	subq.l 	#1,crt0_temp
	bne 	_fill_loop

	cmp.b	#_CPU349,SIM_IDR(crt0_sim_base)
	bne	_fill_bccram

	/* fill QDMM memory */
	movea.l #_FastRam_Start,crt0_ptr3			| get start
	move.l  #_FastRam_Size,crt0_temp 			| get size
	lsr.l   #2,crt0_temp            			| ajust for long word

_QDMMfill_loop:
	clr.l 	(crt0_ptr3)+
	subq.l	#1,crt0_temp
	bne	_QDMMfill_loop
	bra	_dont_fill

	/* fill BCC memory */
_fill_bccram:
	movea.l #_BCCram_Start,crt0_ptr3			| get start
	move.l  #_BCCram_Size,crt0_temp 			| get size
	lsr.l   #2,crt0_temp            			| ajust for long word
_BCCfill_loop:
	clr.l 	(crt0_ptr3)+
	subq.l 	#1,crt0_temp
	bne 	_BCCfill_loop

	*-------------------------------------------------*/
_dont_fill:
	move.b	crt0_csswitch,_AsteccCsSwitch
	move.b	crt0_buswidth,_AsteccBusWidth
	move.l	crt0_cpu_type,_AsteccCpuName

	jmp	SYM(_Init68340)					| Start C code (which never returns)

/*
 * Copy DATA segment, clear BSS segment, set up real stack,
 * initialize heap, start C program.
 * Assume that DATA and BSS sizes are multiples of 4.
 */
	PUBLIC (_CopyDataClearBSSAndStart)
SYM(_CopyDataClearBSSAndStart):
	lea	SYM(_copy_start),a0				| Get start of DATA in RAM
	lea	SYM(_etext),a2					| Get start of DATA in ROM
	cmpl	a0,a2						| Are they the same?
	beq.s	NOCOPY						| Yes, no copy necessary
	lea	SYM(_copy_end),a1				| Get end of DATA in RAM
	bra.s	COPYLOOPTEST					| Branch into copy loop
COPYLOOP:
	movel	a2@+,a0@+					| Copy word from ROM to RAM
COPYLOOPTEST:
	cmpl	a1,a0						| Done?
	bcs.s	COPYLOOP					| No, skip
NOCOPY:

	lea	_clear_start,a0					| Get start of BSS
	lea	_clear_end,a1					| Get end of BSS
	clrl	d0						| Value to set
	bra.s	ZEROLOOPTEST					| Branch into clear loop
ZEROLOOP:
	movel	d0,a0@+						| Clear a word
ZEROLOOPTEST:
	cmpl	a1,a0						| Done?
	bcs.s	ZEROLOOP					| No, skip

	movel	#_stack_init,a7					| set master stack pointer
	movel	d0,a7@-						| environp
	movel	d0,a7@-						| argv
	movel	d0,a7@-						| argc
	jsr	SYM(boot_card)					| Call C main

	PUBLIC (_mainDone)
SYM(_mainDone):
	nop							| Leave spot for breakpoint
	movew	#1,a7						| Force a double bus error
	movel	d0,a7@-						| This should cause a RESET
/*	stop	#0x2700						| Stop with interrupts disabled */
	move.w	#0x2700,sr
	bra.l	SYM(_mainDone)					| Stuck forever

        .align 2
BEGIN_DATA_DCL
        .align 2
	PUBLIC (environ)
SYM (environ):
	.long	0
	PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
	.long	0
END_DATA_DCL

END