m302_int.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

    /* Serial Interface */

  ushort  serial_int_mask;        /* mask register */
  ushort  serial_int_mode;        /* mode register */

    /* reserved */

  uchar  reserved_3[0x74A];



/****************** 68 EN 302 specific registers **********************/
/** only available here if
    M68302_INTERNAL_RAM_BASE_ADD+0x1000=M68EN302_INTERNAL_RAM_BASE_ADD*/

    /* Module Bus Control Registers */

  ushort  mbc;              /* module bus control register MBC */
  ushort  ier;              /* interrupt extension register IER */
  ushort  cser[4];          /* Chip Select extension registers CSERx */
  ushort  pcsr;             /* parity control & status register PCSR */

  ushort  mbc_reserved;

    /* DRAM Controller Registers */

  ushort  dcr;              /* DRAM Configuration register DCR */
  ushort  drfrsh;           /* DRAM Refresh register DRFRSH */
  ushort  dba[2];           /* DRAM Bank Base Address Register */

  uchar  dram_reserved[0x7E8];


    /* Ethernet Controller Registers */

  ushort  ecntrl;            /* Ethernet Control Register */
  ushort  edma;              /* Ethernet DMA Configuration Register */
  ushort  emrblr;            /* Ethernet Max receive buffer length */
  ushort  intr_vect;         /* Interruppt vector register */
  ushort  intr_event;        /* Interruppt event register */
  ushort  intr_mask;         /* Interruppt mask register */
  ushort  ecnfig;            /* Ethernet Configuration */
  ushort  ether_test;        /* Ethernet Test register */
  ushort  ar_cntrl;          /* Address Recognition Control register */

  uchar  eth_reserved[0x1EE];

  uchar  cet[0x200];                  /* CAM Entry Table */
  struct m68302_scc_bd eth_bd[128];   /* Ethernet Buffer Descriptors Table */

};

#define M68302imp_     a_m68302_imp ->

#define M68302imp_a_scc_bd_rx(scc,bd) \
     (struct m68302_scc_bd FAR *)(&(M68302imp_ parm_ram[scc].scc_bd_rx[bd]))
#define M68302imp_a_scc_bd_tx(scc,bd) \
     (struct m68302_scc_bd FAR *)(&(M68302imp_ parm_ram[scc].scc_bd_tx[bd]))

#define M68302imp_scc_rfcr(scc)      (M68302imp_ parm_ram[scc].rfcr)
#define M68302imp_scc_tfcr(scc)      (M68302imp_ parm_ram[scc].tfcr)
#define M68302imp_scc_mrblr(scc)     (M68302imp_ parm_ram[scc].mrblr)
#define M68302imp_scc_rbdn(scc)      (M68302imp_ parm_ram[scc].rbdn)
#define M68302imp_scc_tbdn(scc)      (M68302imp_ parm_ram[scc].tbdn)

#define M68302imp_a_scc_spp(scc)    ((struct m68302_scc_spp FAR *)(M68302imp_ parm_ram[scc].scc_spp))

#define M68302imp_dma_res1        (M68302imp_ dma_res1)
#define M68302imp_dma_mode        (M68302imp_ dma_mode)
#define M68302imp_dma_src         (M68302imp_ dma_src)
#define M68302imp_dma_dest        (M68302imp_ dma_dest)
#define M68302imp_dma_count       (M68302imp_ dma_count)
#define M68302imp_dma_status      (M68302imp_ dma_status)
#define M68302imp_dma_fct_code    (M68302imp_ dma_fct_code)

#define M68302imp_it_mode         (M68302imp_ it_mode)
#define M68302imp_it_pending      (M68302imp_ it_pending)
#define M68302imp_it_mask         (M68302imp_ it_mask)
#define M68302imp_it_inservice    (M68302imp_ it_inservice)

#define M68302imp_cs_base(i)      (M68302imp_ cs[i].base)
#define M68302imp_cs_option(i)    (M68302imp_ cs[i].option)

#define M68302imp_port_control(i)    (M68302imp_ port[i].control)
#define M68302imp_port_direction(i)  (M68302imp_ port[i].direction)
#define M68302imp_port_data(i)       (M68302imp_ port[i].data)

#define M68302imp_timer1_mode        (M68302imp_ t1_mode)
#define M68302imp_timer1_reference   (M68302imp_ t1_reference)
#define M68302imp_timer1_capture     (M68302imp_ t1_capture)
#define M68302imp_timer1_counter     (M68302imp_ t1_counter)
#define M68302imp_timer1_event       (M68302imp_ t1_event)
#define M68302imp_timer3_reference   (M68302imp_ t3_reference)
#define M68302imp_timer3_counter     (M68302imp_ t3_counter)
#define M68302imp_timer2_mode        (M68302imp_ t2_mode)
#define M68302imp_timer2_reference   (M68302imp_ t2_reference)
#define M68302imp_timer2_capture     (M68302imp_ t2_capture)
#define M68302imp_timer2_counter     (M68302imp_ t2_counter)
#define M68302imp_timer2_event       (M68302imp_ t2_event)

#define M68302imp_cp_cmd             (M68302imp_ cp_cmd)

#define M68302imp_scc_mode_reg       (M68302imp_ scc_mode_reg)

#define M68302imp_serial_int_mask    (M68302imp_ serial_int_mask)
#define M68302imp_serial_int_mode    (M68302imp_ serial_int_mode)
#define M68302imp_simask             (M68302imp_serial_int_mask)
#define M68302imp_simode             (M68302imp_serial_int_mode)

#define M68302imp_scon(i)            (M68302imp_ scc_regs[i].scon)
#define M68302imp_scm(i)             (M68302imp_ scc_regs[i].scm)
#define M68302imp_dsr(i)             (M68302imp_ scc_regs[i].dsr)
#define M68302imp_scce(i)            (M68302imp_ scc_regs[i].scce)
#define M68302imp_sccm(i)            (M68302imp_ scc_regs[i].sccm)
#define M68302imp_sccs(i)            (M68302imp_ scc_regs[i].sccs)


/*----------------------------------------------------------------------------*/

#define M68en302imp_mbc              (M68302imp_ mbc)
#define M68en302imp_ier              (M68302imp_ ier)
#define M68en302imp_cser(i)          (M68302imp_ cser[i])
#define M68en302imp_pcsr             (M68302imp_ pcsr)

#define M68en302imp_dcr              (M68302imp_ dcr)
#define M68en302imp_drfrsh           (M68302imp_ drfrsh)
#define M68en302imp_dba(i)           (M68302imp_ dba[i])


#define M68en302imp_ecntrl           (M68302imp_ ecntrl)
#define M68en302imp_edma             (M68302imp_ edma)
#define M68en302imp_emrblr           (M68302imp_ emrblr)
#define M68en302imp_intr_vect        (M68302imp_ intr_vect)
#define M68en302imp_intr_event       (M68302imp_ intr_event)
#define M68en302imp_intr_mask        (M68302imp_ intr_mask)
#define M68en302imp_ecnfig           (M68302imp_ ecnfig)
#define M68en302imp_ether_test       (M68302imp_ ether_test)
#define M68en302imp_ar_cntrl         (M68302imp_ ar_cntrl)

#define M68en302imp_cet              (M68302imp_ cet)

#define M68302imp_a_eth_bd(bd) \
    (struct m68302_scc_bd *)(&(M68302imp_ eth_bd[bd]))

/* PORTS */

#define PA0     0x0001    /* PORT A bit 0 */
#define PA1     0x0002    /* PORT A bit 1 */
#define PA2     0x0004    /* PORT A bit 2 */
#define PA3     0x0008    /* PORT A bit 3 */
#define PA4     0x0010    /* PORT A bit 4 */
#define PA5     0x0020    /* PORT A bit 5 */
#define PA6     0x0040    /* PORT A bit 6 */
#define PA7     0x0080    /* PORT A bit 7 */
#define PA8     0x0100    /* PORT A bit 8 */
#define PA9     0x0200    /* PORT A bit 9 */
#define PA10    0x0400    /* PORT A bit 10 */
#define PA11    0x0800    /* PORT A bit 11 */
#define PA12    0x1000    /* PORT A bit 12 */
#define PA13    0x2000    /* PORT A bit 13 */
#define PA14    0x4000    /* PORT A bit 14 */
#define PA15    0x8000    /* PORT A bit 15 */

#define PB0     0x0001    /* PORT B bit 0 */
#define PB1     0x0002    /* PORT B bit 1 */
#define PB2     0x0004    /* PORT B bit 2 */
#define PB3     0x0008    /* PORT B bit 3 */
#define PB4     0x0010    /* PORT B bit 4 */
#define PB5     0x0020    /* PORT B bit 5 */
#define PB6     0x0040    /* PORT B bit 6 */
#define PB7     0x0080    /* PORT B bit 7 */
#define PB8     0x0100    /* PORT B bit 8 */
#define PB9     0x0200    /* PORT B bit 9 */
#define PB10    0x0400    /* PORT B bit 10 */

#define PB11    0x0800    /* PORT B bit 11 */

/* MODULE BUS CONTROL (MBCTL) */

#define MBC_BCE   0x8000
#define MBC_MFC2  0x4000
#define MBC_MFC1  0x2000
#define MBC_MFC0  0x1000
#define MBC_BB    0x0800
#define MBC_PPE   0x0400
#define MBC_PM9   0x0200
#define MBC_PM8   0x0100
#define MBC_PM7   0x0080
#define MBC_PM6   0x0040
#define MBC_PM5   0x0020
#define MBC_PM4   0x0010
#define MBC_PM3   0x0008
#define MBC_PM2   0x0004
#define MBC_PM1   0x0002
#define MBC_PM0   0x0001

  /* DRAM CONFIGURATION REG (DCR) */

#define DCR_SU0   0x0001
#define DCR_SU1   0x0002
#define DCR_WP0   0x0004
#define DCR_WP1   0x0008
#define DCR_W0    0x0010
#define DCR_W1    0x0020
#define DCR_P0    0x0040
#define DCR_P1    0x0080
#define DCR_PE0   0x0100
#define DCR_PE1   0x0200
#define DCR_E0    0x0400
#define DCR_E1    0x0800

/* M68302 INTERNAL RAM BASE ADDRESS INSTALLATION */

#define M68302_ram_base_add_install(base_reg_add,ram_base_add) \
  do { \
    *((ushort *)base_reg_add) =  (ushort)(ram_base_add >> 12); \
   a_m68302_imp = (struct m68302_imp *)ram_base_add; \
  } while (0)

#define M68302_system_ctrl_reg_install(val) (*((ulong *)M68302_SCR_ADD) = val)

  /* INTERRUPTION */

  /* Interrupt mode selection */

#define M68302_it_mode_install(mode,vector_bank, \
  extvect1,extvect6,extvect7,edgetrig1,edgetrig6,edgetrig7) \
    M68302imp_it_mode = 0 | (mode << 15) | (vector_bank << 5) | \
        (extvect7 << 14) | (extvect6 << 13) | (extvect1 <<12) | \
        (edgetrig7 << 10) | (edgetrig6 << 9)|(edgetrig1 << 8)

  /* CHIP SELECTION */

  /* 'read_write' support values :
   *
   *  M68302_CS_READ_ONLY      for read only memory access chip select
   *  M68302_CS_READ_WRITE_ONLY  for write only memory access chip select
   *  M68302_CS_READ_AND_WRITE  for read & write memory access chip select
   *
   *  'nb_wait_state' : number of wait-state(s) from 0 to 6, 7 for external
   *
   */
#define M68302_CS_READ_ONLY      0x02 /* read only memory access */
#define M68302_CS_WRITE_ONLY     0x22 /* write only memory access */
#define M68302_CS_READ_AND_WRITE 0x00 /* read and write memory access */


#define M68302_cs_install(cs_nb,base_add,range,nb_wait_state,read_write) \
  do { \
    M68302imp_cs_option(cs_nb) = (((~(range - 1)) >> 11) & 0x1FFC) | \
      (nb_wait_state << 13) | (read_write & 0x2); \
    M68302imp_cs_base(cs_nb) = (((base_add >> 11) & 0x1FFC) | \
      ((read_write >> 4) & 0x2) | 1); \
  } while (0)

#define M68302_set_cs_br(base_add, read_write)  \
    ((((base_add) >> 11) & 0x1FFC) | (((read_write) >> 4) & 0x2) | 1)

#define M68302_set_cs_or(range, nb_wait_state, read_write) \
   ((((~(range - 1)) >> 11) & 0x1FFC) | \
       ((nb_wait_state) << 13) | ((read_write) & 0x2))

#define M68302_get_cs_br(cs)  \
    (((ulong)((M68302imp_cs_base(cs)) & 0x1FFC)) << 11 )

/* DRAM */

#define M68en302_dram_install(bank,base_add,range)  \
  M68en302imp_dba (bank)  = \
    (((base_add >> 8) & 0xFE00) | (((~(range-1))>>16) & 0x007E) | 1)

#endif