m302_int.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*
 *  Implements the Motorola 68302 multi-protocol chip parameter
 *  definition header.
 *
 *  $Id: m302_int.h,v 1.1 2000/12/14 17:53:53 joel Exp $
 */

#ifndef __M302_INT_h
#define __M302_INT_h

#ifndef uchar
#define uchar unsigned char
#endif
#ifndef ushort
#define ushort unsigned short
#endif
#ifndef ulong
#define ulong unsigned long
#endif

/* Ethernet Control Register ECNTRL */
#define ECNTRL_BIT_RESET    0x0001
#define ECNTRL_BIT_ETHER_EN  0x0002
#define ECNTRL_BIT_GTS      0x0004

/* Ethernet DMA Configuration Status Register EDMA */
#define EDMA_BDERR_MASK      0xFE00

#define EDMA_BDSIZE_MASK      0x00C0
#define EDMA_BDSIZE_8T_120R    0x0000
#define EDMA_BDSIZE_16T_112R  0x0040
#define EDMA_BDSIZE_32T_96R    0x0080
#define EDMA_BDSIZE_64T_64R    0x00C0

#define EDMA_BIT_TSRLY      0x0020

#define EDMA_WMRK_MASK      0x0018
#define EDMA_WMRK_8FIFO      0x0000
#define EDMA_WMRK_16FIFO    0x0008
#define EDMA_WMRK_24FIFO    0x0010
#define EDMA_WMRK_32FIFO    0x0018

#define EDMA_BLIM_MASK      0x0007
#define EDMA_BLIM_8ACCESS    0x0003


/* Ethernet Maximum Receive Buffer Length EMRBLR */
#define EMRBLR_MASK          0x07FFE

/* Interrupt Vector Register IVEC */
#define IVEC_BIT_VG          0x0100
#define IVEC_INV_MASK        0x00FF

/* Interrupt Event Register INTR_EVENT */
#define INTR_EVENT_BIT_RXB      0x0001
#define INTR_EVENT_BIT_TXB      0x0002
#define INTR_EVENT_BIT_BSY      0x0004
#define INTR_EVENT_BIT_RFINT    0x0008
#define INTR_EVENT_BIT_TFINT    0x0010
#define INTR_EVENT_BIT_EBERR    0x0020
#define INTR_EVENT_BIT_BOD      0x0040
#define INTR_EVENT_BIT_GRA      0x0080
#define INTR_EVENT_BIT_BABT      0x0100
#define INTR_EVENT_BIT_BABR      0x0200
#define INTR_EVENT_BIT_HBERR    0x0400

/* Interrupt Mask Register INTR_MASK */
#define INTR_MASK_BIT_RXIEN      0x0001
#define INTR_MASK_BIT_TXIEN      0x0002
#define INTR_MASK_BIT_BSYEN      0x0004
#define INTR_MASK_BIT_RFIEN      0x0008
#define INTR_MASK_BIT_TFIEN      0x0010
#define INTR_MASK_BIT_EBERREN    0x0020
#define INTR_MASK_BIT_BODEN      0x0040
#define INTR_MASK_BIT_GRAEN      0x0080
#define INTR_MASK_BIT_BTEN      0x0100
#define INTR_MASK_BIT_BREN      0x0200
#define INTR_MASK_BIT_HBEEN      0x0400

/* Ethernet Configuration ECNFIG */
#define ECNFIG_BIT_LOOP          0x0001
#define ECNFIG_BIT_FDEN          0x0002
#define ECNFIG_BIT_HBC          0x0004
#define ECNFIG_BIT_RDT          0x0008

/* Ethernet Test ETHER_TEST */
#define ETHER_TEST_BIT_TWS      0x0001
#define ETHER_TEST_BIT_RWS      0x0002
#define ETHER_TEST_BIT_DRTY      0x0004
#define ETHER_TEST_BIT_COLL      0x0008
#define ETHER_TEST_BIT_SLOT      0x0010
#define ETHER_TEST_BIT_TRND      0x0020
#define ETHER_TEST_BIT_TBO      0x0040
#define ETHER_TEST_BIT_RNGT      0x0080
#define ETHER_TEST_REV_MASK      0xF000

/* Ethernet AR Control Registere AR_CNTRL */
#define AR_CNTRL_BIT_PROM        0x0400
#define AR_CNTRL_BIT_PA_REJ      0x0800
#define AR_CNTRL_BIT_NO_BROADCAST  0x1000
#define AR_CNTRL_BIT_MULTI1      0x2000
#define AR_CNTRL_BIT_INDEX_EN    0x4000
#define AR_CNTRL_BIT_HASH_EN    0x8000

#define AR_CNTRL_MULTI_MASK      (AR_CNTRL_BIT_MULTI0 | AR_CNTRL_BIT_MULTI1)


/* Ethernet buffer Status TX */
#define BUF_STAT_CARRIER_LOST    0x0001
#define BUF_STAT_UNDERRUN        0x0002
#define BUF_STAT_RETRANS_COUNT  0x003C
#define BUF_STAT_RETRY_LIMIT    0x0040
#define BUF_STAT_LATE_COLLISION  0x0080
#define BUF_STAT_HEARTBIT        0x0100
#define BUF_STAT_DEFER          0x0200
#define BUF_STAT_TX_CRC          0x0400
#define BUF_STAT_LAST            0x0800
#define BUF_STAT_INTERRUPT      0x1000
#define BUF_STAT_WRAP            0x2000
#define BUF_STAT_TO              0x4000
#define BUF_STAT_READY          0x8000


/* Ethernet buffer Status RX */
#define BUF_STAT_COLLISION      0x0001
#define BUF_STAT_OVERRUN        0x0002
#define BUF_STAT_CRC_ERROR      0x0004
#define BUF_STAT_SHORT          0x0008
#define BUF_STAT_NONALIGNED      0x0010
#define BUF_STAT_LONG            0x0020
#define BUF_STAT_FIRST_IN_FRAME  0x0400
#define BUF_STAT_EMPTY          0x8000

  /* SCC Buffer Descriptor structure
  ----------------------------------*/

struct m68302_scc_bd {
  ushort      stat_ctrl;
  ushort      data_lgth;
  uchar      *p_buffer;
};

#define M68302_scc_bd_stat_ctrl(p) \
    (((struct m68302_scc_bd *)(p)) -> stat_ctrl)
#define M68302_scc_bd_data_lgth(p) \
    (((struct m68302_scc_bd *)(p)) -> data_lgth)
#define M68302_scc_bd_p_buffer(p)  \
   (((struct m68302_scc_bd *)(p)) -> p_buffer)

struct m68302_imp {

/* BASE : user data memory  */

  uchar  user_data[0x240];        /* 0x240 bytes user data */
  uchar  user_reserved[0x1c0];    /* empty till 0x400 */

/* BASE + 400H: PARAMETER RAM */
  struct {
    struct m68302_scc_bd scc_bd_rx[8];  /* Rx buffer descriptors */
    struct m68302_scc_bd scc_bd_tx[8];  /* Tx buffer descriptors */

    uchar      rfcr;        /* Rx function code */
    uchar      tfcr;        /* Tx function code */
    ushort     mrblr;        /* maximum Rx buffer length */
    ushort     rist;        /* internal state */
    uchar      res1;
    uchar      rbdn;        /* Rx internal buffer number */
    ulong      ridp;
    ushort     ribc;
    ushort     rtmp;
    ushort     tist;
    uchar      res2;
    uchar      tbdn;        /* Tx internal buffer number */
    ulong      tidp;
    ushort     tibc;
    ushort     ttmp;

    unsigned char  scc_spp  [0x64];    /* SCC specific parameters */
  } parm_ram [3];

  uchar reserved_1 [0x100];

/* BASE + 800H: INTERNAL REGISTERS */

    /* DMA */

  ushort  dma_res1;           /* reserved */
  ushort  dma_mode;           /* dma mode reg */
  ulong   dma_src;            /* dma source */
  ulong   dma_dest;           /* dma destination */
  ushort  dma_count;          /* dma byte count */
  uchar   dma_status;         /* dma status */
  uchar   dma_res2;           /* reserved */
  uchar   dma_fct_code;       /* dma function code */
  uchar   dma_res3;           /* reserved */

    /* Interrupt Controller */

  ushort  it_mode;            /* interrupt mode register */
  ushort  it_pending;         /* interrupt pending register */
  ushort  it_mask;            /* interrupt mask register */
  ushort  it_inservice;       /* interrupt in service register */
  ulong   it_reserved;        /* reserved */

    /* Parallel I/O */

  struct {
    ushort  control;         /* port control register */
    ushort  direction;       /* port data direction register */
    ushort  data;            /* port data value register */
  } port[2];

  ushort  p_reserved;        /* reserved */

    /* Chip Select */

  ulong  cs_reserved;

  struct {
    ushort  base;            /* chip select base register */
    ushort  option;          /* chip select option register */
  } cs[4];

    /* Timer */

  ushort  t1_mode;             /* timer 1 mode register */
  ushort  t1_reference;        /* timer 1 reference register */
  ushort  t1_capture;          /* timer 1 capture register */
  ushort  t1_counter;          /* timer 1 counter */
  uchar   tim_res1;            /* reserved */
  uchar   t1_event;            /* timer 1 event */

  ushort  t3_reference;        /* timer 3 reference register */
  ushort  t3_counter;          /* timer 3 counter */
  ushort  tim_res2;            /* reserved */

  ushort  t2_mode;              /* timer 2 mode register */
  ushort  t2_reference;         /* timer 2 reference register */
  ushort  t2_capture;           /* timer 2 capture register */
  ushort  t2_counter;           /* timer 2 counter */
  uchar   tim_res3;             /* reserved */
  uchar   t2_event;             /* timer 2 event */
  ushort  tim_res4[3];          /* reserved */

    /* command register */

  uchar  cp_cmd;                /* communication processor command register */
  uchar  cp_cmd_res;            /* reserved */

    /* reserved */

  uchar  reserved_2[0x1e];

    /* SCC registers */

  struct scc_regs {
    ushort  resvd;           /* reserved */
    ushort  scon;            /* SCC configuration register */
    ushort  scm;             /* SCC mode register */
    ushort  dsr;             /* SCC sync register */
    uchar   scce;            /* SCC event register */
    uchar   res1;            /* reserved */
    uchar   sccm;            /* SCC mask register */
    uchar   res2;            /* reserved */
    uchar   sccs;            /* SCC status register */
    uchar   res3;            /* reserved */
    ushort  res4;            /* reserved */
  } scc_regs[3];

    /* SP (SCP + SMI) */

  ushort  scc_mode_reg;          /* scp, smi mode + clock control */