📄 irq.c
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if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { _CPU_ISR_Enable(level); return 0; } } if (is_isa_irq(irq->name)) { /* * disable interrupt at PIC level */ BSP_irq_disable_at_i8259s (irq->name); } if (is_pci_irq(irq->name)) { /* * disable interrupt at OPENPIC level */ openpic_disable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); } if (is_processor_irq(irq->name)) { /* * disable exception at processor level */ } /* * Disable interrupt on device */ irq->off(irq); /* * restore the default irq value */ if( !vchain ) { /* single handler vector... */ rtems_hdl_tbl[irq->name] = default_rtems_entry; } else { if( pchain ) { /* non-first handler being removed */ pchain->next_handler = vchain->next_handler; } else { /* first handler isn't malloc'ed, so just overwrite it. Since the contents of vchain are being struct copied, vchain itself goes away */ rtems_hdl_tbl[irq->name]= *vchain; } free(vchain); } _CPU_ISR_Enable(level); return 1;}/* * RTEMS Global Interrupt Handler Management Routines */int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config){ int i; unsigned int level; /* * Store various code accelerators */ internal_config = config; default_rtems_entry = config->defaultEntry; rtems_hdl_tbl = config->irqHdlTbl; _CPU_ISR_Disable(level); /* * set up internal tables used by rtems interrupt prologue */ /* * start with ISA IRQ */ compute_i8259_masks_from_prio (); for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { BSP_irq_enable_at_i8259s (i); /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */ { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->on(vchain); } } } else { /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->off(vchain); } } BSP_irq_disable_at_i8259s (i); } } /* * must enable slave pic anyway */ BSP_irq_enable_at_i8259s (2); /* * continue with PCI IRQ */ for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) { /* * Note that openpic_set_priority() sets the TASK priority of the PIC */ openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET, internal_config->irqPrioTbl[i]); if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */ { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->on(vchain); } } } else { /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->off(vchain); } } openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); } } /* * Must enable PCI/ISA bridge IRQ */ openpic_enable_irq (0); /* * finish with Processor exceptions handled like IRQ */ for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */ { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->on(vchain); } } } else { /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->off(vchain); } } } } _CPU_ISR_Enable(level); return 1;}int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config){ *config = internal_config; return 0;} int _BSP_vme_bridge_irq = -1; unsigned BSP_spuriousIntr = 0;/* * High level IRQ handler called from shared_raw_irq_code_entry */void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum){ register unsigned int irq; register unsigned isaIntr; /* boolean */ register unsigned oldMask = 0; /* old isa pic masks */ register unsigned newMask; /* new isa pic masks */ register unsigned msr; register unsigned new_msr; if (excNum == ASM_DEC_VECTOR) { _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); rtems_hdl_tbl[BSP_DECREMENTER].hdl(); _CPU_MSR_SET(msr); return; } irq = openpic_irq(0); if (irq == OPENPIC_VEC_SPURIOUS) { ++BSP_spuriousIntr; return; } isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); if (isaIntr) { /* * Acknowledge and read 8259 vector */ irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG); /* * store current PIC mask */ oldMask = i8259s_cache; newMask = oldMask | irq_mask_or_tbl [irq]; i8259s_cache = newMask; outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); BSP_irq_ack_at_i8259s (irq); openpic_eoi(0); } _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); /* rtems_hdl_tbl[irq].hdl(); */ { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[irq]; ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->hdl(); } } _CPU_MSR_SET(msr); if (isaIntr) { i8259s_cache = oldMask; outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); } else {#ifdef BSP_PCI_VME_DRIVER_DOES_EOI /* leave it to the VME bridge driver to do EOI, so * it can re-enable the openpic while handling * VME interrupts (-> VME priorities in software) */ if (_BSP_vme_bridge_irq != irq)#endif openpic_eoi(0); }} void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx){ /* * Process pending signals that have not already been * processed by _Thread_Displatch. This happens quite * unfrequently : the ISR must have posted an action * to the current running thread. */ if ( _Thread_Do_post_task_switch_extension || _Thread_Executing->do_post_task_switch_extension ) { _Thread_Executing->do_post_task_switch_extension = FALSE; _API_extensions_Run_postswitch(); } /* * I plan to process other thread related events here. * This will include DEBUG session requested from keyboard... */}
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