universe.c

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

   /*
    * VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO 
    * register. Map the VME base address 0x4000000 to local memory address 0x0
    */
   PCI_bus_write( &UNIVERSE->VSI0_TO, 0x7C000000 );

   /*
    * Set the VMEbus Slave Image 0 Control register with write posted,
    * read prefetch and AM code set for program, data, supervisor and user mode
    */
   PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 );   
#endif

   /*
    * Set the VMEbus Master Control register with retry forever, 256 bytes
    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes 
    * aligned burst size and PCI bus number to be zero
    */
   PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );

   /*
    * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
    * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
    * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );   
    */
   
   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
   PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
   PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
   PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );


#if 0
   /*
    * Set the PCI Slave Image 0 Control register with posted write enable,
    * 32 bit data width, A32 VMEbus address base, AM code to be data, 
    * none-privilleged, single and BLT cycles on VME bus with PCI 
    * bus memory space.
   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 );   
    */
   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );   

   /*
    * Set the PCI Slave Image 0 Base Address to be 
    * 0x0 on LSI0_BS register.
    */
   PCI_bus_write( &UNIVERSE->LSI0_BS, 0x00FF0000 );

   /*
    * Set the PCI Slave Image 0 Bound Address to be 
    * 0xFFFFF000 on VSI0_BD register.
    */
   PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 );   

   /*
    * Set the PCI Slave Image 0 Translation Offset to be 
    * 0x0 on VSI0_TO register.
    * Note: If the actual VME address is bigger than 0x40000000, we need 
    *   to set the PCI Slave Image 0 Translation Offset = 0x40000000
    *   register.  
    *   i.e. if actual VME ADRR = 0x50000000, then we 
    *     need to subtract it by 0x40000000 and set 
    *      the LSI0_T0 register to be 0x40000000 and then
    *     perform a PCI data access by adding 0xC0000000 to
    *     0x10000000 -- which is came form the result of
    *     (0x50000000 - 0x40000000). 
    */
   PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 );   
#endif

   /* 
    * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
    * BI-Mode VMEbus accesses can be made. 
    */

   universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );

   if (universe_temp_value & 0x100000)
     PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
}

/*
 * Set the slave VME base address to the specified base address.
 * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
 *       Slave Image 0 registers.
 */
void set_vme_base_address (
  rtems_unsigned32 base_address 
)
{  
  volatile rtems_unsigned32 temp;

  /*
   * Calculate the current size of the Slave VME image 0
   */
  temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - 
          ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);

  /*
   * Set the VMEbus Slave Image 0 Base Address to be 
   * the specifed base address on VSI0_BS register.
   */
   PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );   

  /*
   * Update the VMEbus Slave Image 0 Bound Address.
   */
  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );

  /*
   * Update the VMEbus Slave Image 0 Translation Offset
   */
  temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
  PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
}

/*
 * Gets the VME base address
 */
rtems_unsigned32 get_vme_base_address ()
{  
  volatile rtems_unsigned32 temp;

  temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
  temp &= 0xFFFFF000;
  return (temp);
}

rtems_unsigned32 get_vme_slave_size()
{
  volatile rtems_unsigned32 temp;
  temp  =  PCI_bus_read( &UNIVERSE->VSI0_BD);
  temp &= 0xFFFFF000;
  temp  = temp - get_vme_base_address ();
  return temp;
}

/*
 * Set the size of the VME slave image
 * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
 */
void set_vme_slave_size (rtems_unsigned32 size)
{  
  volatile rtems_unsigned32 temp;

  if (size<0) 
    size = 0;
  
  if (size > 0x17FFFFF) 
    size = 0x17FFFFF;
   
  /*
   * Read the VME slave image base address
   */
  temp = get_vme_base_address ();

  /*
   * Update the VMEbus Slave Image 0 Bound Address.
   */
  temp = temp + (size & 0xFFFFF000);
  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
}

#if 0
/* XXXXX */
/*
 * Returns the 16 bit location specified by vme_ptr, which must be a
 * pointer to VME D16 space
 */
rtems_unsigned16 get_vme(
  rtems_unsigned16 *vme_ptr
)
{
  rtems_unsigned16 result;

  if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF)
  {
    /*
     * LSI0_TO register to 0x3EFFF000 if it had not been updated already
     */
    if (( PCI_bus_read( &UNIVERSE->LSI0_TO ) & 0xFFFFF000) != 0x3EFFF000)
         PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );

    result = (*(rtems_unsigned16 *)(
               ((rtems_unsigned32)vme_ptr - 0x3EFFF000)+
                PPCN_60X_PCI_MEM_BASE) );
   }
   else
     result = (*(rtems_unsigned16 *)
                ((rtems_unsigned32)vme_ptr+PPCN_60X_PCI_MEM_BASE));

   return result;
}

/*
 * Stores the 16 bit word at the location specified by vme_ptr, which must
 * be a pointer to VME D16 space
 */
void put_vme(
  rtems_unsigned16 *vme_ptr,
  rtems_unsigned16 value
)
{ 

  if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) {
    /* 
     * LSI0_TO register to 0x3EFFF000 if it had not been updated already
     */
     if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000)
       PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );
   
    *(rtems_unsigned16 *) (((rtems_unsigned32)vme_ptr - 0x3EFFF000) + 
                            PPCN_60X_PCI_MEM_BASE) = value;
   }
   else
      *(rtems_unsigned16 *)((rtems_unsigned32)vme_ptr + 
                             PPCN_60X_PCI_MEM_BASE) = value;
}
#endif