commproc.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*
 * MPC8xx Communication Processor Module.
 * Copyright (c) 1997 Dan Malek ([e-mail])
 *
 * This file contains structures and information for the communication
 * processor channels.  Some CPM control and status is available
 * throught the MPC8xx internal memory map.  See immap.h for details.
 * This file only contains what I need for the moment, not the total
 * CPM capabilities.  I (or someone else) will add definitions as they
 * are needed.  -- Dan
 *
 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
 * bytes of the DP RAM and relocates the I2C parameter area to the
 * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
 * or other use.
 */
#ifndef __CPM_8XX__
#define __CPM_8XX__

#include <bsp/8xx_immap.h>

/* CPM Command register.
*/
#define CPM_CR_RST	((unsigned short)0x8000)
#define CPM_CR_OPCODE	((unsigned short)0x0f00)
#define CPM_CR_CHAN	((unsigned short)0x00f0)
#define CPM_CR_FLG	((unsigned short)0x0001)

/* Some commands (there are more...later)
*/
#define CPM_CR_INIT_TRX		((unsigned short)0x0000)
#define CPM_CR_INIT_RX		((unsigned short)0x0001)
#define CPM_CR_INIT_TX		((unsigned short)0x0002)
#define CPM_CR_STOP_TX		((unsigned short)0x0004)
#define CPM_CR_RESTART_TX	((unsigned short)0x0006)
#define CPM_CR_SET_GADDR	((unsigned short)0x0008)

/* Channel numbers.
*/
#define CPM_CR_CH_SCC1	((unsigned short)0x0000)
#define CPM_CR_CH_I2C	((unsigned short)0x0001)	/* I2C and IDMA1 */
#define CPM_CR_CH_SCC2	((unsigned short)0x0004)
#define CPM_CR_CH_SPI	((unsigned short)0x0005)	/* SPI / IDMA2 / Timers */
#define CPM_CR_CH_SCC3	((unsigned short)0x0008)
#define CPM_CR_CH_SMC1	((unsigned short)0x0009)	/* SMC1 / DSP1 */
#define CPM_CR_CH_SCC4	((unsigned short)0x000c)
#define CPM_CR_CH_SMC2	((unsigned short)0x000d)	/* SMC2 / DSP2 */

#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))

/* The dual ported RAM is multi-functional.  Some areas can be (and are
 * being) used for microcode.  There is an area that can only be used
 * as data ram for buffer descriptors, which is all we use right now.
 * Currently the first 512 and last 256 bytes are used for microcode.
 */
#define CPM_DATAONLY_BASE	((unsigned int)0x0800)
#define CPM_DATAONLY_SIZE	((unsigned int)0x0700)
#define CPM_DP_NOSPACE		((unsigned int)0x7fffffff)

/* Export the base address of the communication processor registers
 * and dual port ram.
 */
extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
unsigned int		m8xx_cpm_dpalloc(unsigned int size);
unsigned int		m8xx_cpm_hostalloc(unsigned int size);
void			m8xx_cpm_setbrg(unsigned int brg, unsigned int rate);

/* Buffer descriptors used by many of the CPM protocols.
*/
typedef struct cpm_buf_desc {
	unsigned short	cbd_sc;		/* Status and Control */
	unsigned short	cbd_datlen;	/* Data length in buffer */
	unsigned int	cbd_bufaddr;	/* Buffer address in host memory */
} cbd_t;

#define BD_SC_EMPTY	((unsigned short)0x8000)	/* Recieve is empty */
#define BD_SC_READY	((unsigned short)0x8000)	/* Transmit is ready */
#define BD_SC_WRAP	((unsigned short)0x2000)	/* Last buffer descriptor */
#define BD_SC_INTRPT	((unsigned short)0x1000)	/* Interrupt on change */
#define BD_SC_CM	((unsigned short)0x0200)	/* Continous mode */
#define BD_SC_ID	((unsigned short)0x0100)	/* Rec'd too many idles */
#define BD_SC_P		((unsigned short)0x0100)	/* xmt preamble */
#define BD_SC_BR	((unsigned short)0x0020)	/* Break received */
#define BD_SC_FR	((unsigned short)0x0010)	/* Framing error */
#define BD_SC_PR	((unsigned short)0x0008)	/* Parity error */
#define BD_SC_OV	((unsigned short)0x0002)	/* Overrun */
#define BD_SC_CD	((unsigned short)0x0001)	/* ?? */

/* Parameter RAM offsets.
*/
#define PROFF_SCC1	((unsigned int)0x0000)
#define PROFF_SCC2	((unsigned int)0x0100)
#define PROFF_SCC3	((unsigned int)0x0200)
#define PROFF_SMC1	((unsigned int)0x0280)
#define PROFF_SCC4	((unsigned int)0x0300)
#define PROFF_SMC2	((unsigned int)0x0380)

/* Define enough so I can at least use the serial port as a UART.
 */
typedef struct smc_uart {
	unsigned short	smc_rbase;	/* Rx Buffer descriptor base address */
	unsigned short	smc_tbase;	/* Tx Buffer descriptor base address */
	unsigned char	smc_rfcr;	/* Rx function code */
	unsigned char	smc_tfcr;	/* Tx function code */
	unsigned short	smc_mrblr;	/* Max receive buffer length */
	unsigned int	smc_rstate;	/* Internal */
	unsigned int	smc_idp;	/* Internal */
	unsigned short	smc_rbptr;	/* Internal */
	unsigned short	smc_ibc;	/* Internal */
	unsigned int	smc_rxtmp;	/* Internal */
	unsigned int	smc_tstate;	/* Internal */
	unsigned int	smc_tdp;	/* Internal */
	unsigned short	smc_tbptr;	/* Internal */
	unsigned short	smc_tbc;	/* Internal */
	unsigned int	smc_txtmp;	/* Internal */
	unsigned short	smc_maxidl;	/* Maximum idle characters */
	unsigned short	smc_tmpidl;	/* Temporary idle counter */
	unsigned short	smc_brklen;	/* Last received break length */
	unsigned short	smc_brkec;	/* rcv'd break condition counter */
	unsigned short	smc_brkcr;	/* xmt break count register */
	unsigned short	smc_rmask;	/* Temporary bit mask */
} smc_uart_t;

/* Function code bits.
*/
#define SMC_EB	((unsigned char)0x10)	/* Set big endian byte order */

/* SMC uart mode register.
*/
#define	SMCMR_REN	((unsigned short)0x0001)
#define SMCMR_TEN	((unsigned short)0x0002)
#define SMCMR_DM	((unsigned short)0x000c)
#define SMCMR_SM_GCI	((unsigned short)0x0000)
#define SMCMR_SM_UART	((unsigned short)0x0020)
#define SMCMR_SM_TRANS	((unsigned short)0x0030)
#define SMCMR_SM_MASK	((unsigned short)0x0030)
#define SMCMR_PM_EVEN	((unsigned short)0x0100)	/* Even parity, else odd */
#define SMCMR_PEN	((unsigned short)0x0200)	/* Parity enable */
#define SMCMR_SL	((unsigned short)0x0400)	/* Two stops, else one */
#define SMCR_CLEN_MASK	((unsigned short)0x7800)	/* Character length */
#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)

/* SMC Event and Mask register.
*/
#define	SMCM_TXE	((unsigned char)0x10)
#define	SMCM_BSY	((unsigned char)0x04)
#define	SMCM_TX		((unsigned char)0x02)
#define	SMCM_RX		((unsigned char)0x01)

/* Baud rate generators.
*/
#define CPM_BRG_RST		((unsigned int)0x00020000)
#define CPM_BRG_EN		((unsigned int)0x00010000)
#define CPM_BRG_EXTC_INT	((unsigned int)0x00000000)
#define CPM_BRG_EXTC_CLK2	((unsigned int)0x00004000)
#define CPM_BRG_EXTC_CLK6	((unsigned int)0x00008000)
#define CPM_BRG_ATB		((unsigned int)0x00002000)
#define CPM_BRG_CD_MASK		((unsigned int)0x00001ffe)
#define CPM_BRG_DIV16		((unsigned int)0x00000001)

/* SCCs.
*/
#define SCC_GSMRH_IRP		((unsigned int)0x00040000)
#define SCC_GSMRH_GDE		((unsigned int)0x00010000)
#define SCC_GSMRH_TCRC_CCITT	((unsigned int)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC	((unsigned int)0x00004000)
#define SCC_GSMRH_TCRC_HDLC	((unsigned int)0x00000000)
#define SCC_GSMRH_REVD		((unsigned int)0x00002000)
#define SCC_GSMRH_TRX		((unsigned int)0x00001000)
#define SCC_GSMRH_TTX		((unsigned int)0x00000800)
#define SCC_GSMRH_CDP		((unsigned int)0x00000400)
#define SCC_GSMRH_CTSP		((unsigned int)0x00000200)
#define SCC_GSMRH_CDS		((unsigned int)0x00000100)
#define SCC_GSMRH_CTSS		((unsigned int)0x00000080)
#define SCC_GSMRH_TFL		((unsigned int)0x00000040)
#define SCC_GSMRH_RFW		((unsigned int)0x00000020)
#define SCC_GSMRH_TXSY		((unsigned int)0x00000010)
#define SCC_GSMRH_SYNL16	((unsigned int)0x0000000c)
#define SCC_GSMRH_SYNL8		((unsigned int)0x00000008)
#define SCC_GSMRH_SYNL4		((unsigned int)0x00000004)
#define SCC_GSMRH_RTSM		((unsigned int)0x00000002)
#define SCC_GSMRH_RSYN		((unsigned int)0x00000001)

#define SCC_GSMRL_SIR		((unsigned int)0x80000000)	/* SCC2 only */
#define SCC_GSMRL_EDGE_NONE	((unsigned int)0x60000000)
#define SCC_GSMRL_EDGE_NEG	((unsigned int)0x40000000)
#define SCC_GSMRL_EDGE_POS	((unsigned int)0x20000000)
#define SCC_GSMRL_EDGE_BOTH	((unsigned int)0x00000000)
#define SCC_GSMRL_TCI		((unsigned int)0x10000000)
#define SCC_GSMRL_TSNC_3	((unsigned int)0x0c000000)
#define SCC_GSMRL_TSNC_4	((unsigned int)0x08000000)
#define SCC_GSMRL_TSNC_14	((unsigned int)0x04000000)
#define SCC_GSMRL_TSNC_INF	((unsigned int)0x00000000)
#define SCC_GSMRL_RINV		((unsigned int)0x02000000)
#define SCC_GSMRL_TINV		((unsigned int)0x01000000)
#define SCC_GSMRL_TPL_128	((unsigned int)0x00c00000)
#define SCC_GSMRL_TPL_64	((unsigned int)0x00a00000)
#define SCC_GSMRL_TPL_48	((unsigned int)0x00800000)
#define SCC_GSMRL_TPL_32	((unsigned int)0x00600000)
#define SCC_GSMRL_TPL_16	((unsigned int)0x00400000)
#define SCC_GSMRL_TPL_8		((unsigned int)0x00200000)
#define SCC_GSMRL_TPL_NONE	((unsigned int)0x00000000)
#define SCC_GSMRL_TPP_ALL1	((unsigned int)0x00180000)
#define SCC_GSMRL_TPP_01	((unsigned int)0x00100000)
#define SCC_GSMRL_TPP_10	((unsigned int)0x00080000)
#define SCC_GSMRL_TPP_ZEROS	((unsigned int)0x00000000)
#define SCC_GSMRL_TEND		((unsigned int)0x00040000)
#define SCC_GSMRL_TDCR_32	((unsigned int)0x00030000)
#define SCC_GSMRL_TDCR_16	((unsigned int)0x00020000)
#define SCC_GSMRL_TDCR_8	((unsigned int)0x00010000)
#define SCC_GSMRL_TDCR_1	((unsigned int)0x00000000)
#define SCC_GSMRL_RDCR_32	((unsigned int)0x0000c000)
#define SCC_GSMRL_RDCR_16	((unsigned int)0x00008000)
#define SCC_GSMRL_RDCR_8	((unsigned int)0x00004000)
#define SCC_GSMRL_RDCR_1	((unsigned int)0x00000000)
#define SCC_GSMRL_RENC_DFMAN	((unsigned int)0x00003000)
#define SCC_GSMRL_RENC_MANCH	((unsigned int)0x00002000)
#define SCC_GSMRL_RENC_FM0	((unsigned int)0x00001000)
#define SCC_GSMRL_RENC_NRZI	((unsigned int)0x00000800)
#define SCC_GSMRL_RENC_NRZ	((unsigned int)0x00000000)
#define SCC_GSMRL_TENC_DFMAN	((unsigned int)0x00000600)
#define SCC_GSMRL_TENC_MANCH	((unsigned int)0x00000400)
#define SCC_GSMRL_TENC_FM0	((unsigned int)0x00000200)
#define SCC_GSMRL_TENC_NRZI	((unsigned int)0x00000100)
#define SCC_GSMRL_TENC_NRZ	((unsigned int)0x00000000)
#define SCC_GSMRL_DIAG_LE	((unsigned int)0x000000c0)	/* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO	((unsigned int)0x00000080)
#define SCC_GSMRL_DIAG_LOOP	((unsigned int)0x00000040)
#define SCC_GSMRL_DIAG_NORM	((unsigned int)0x00000000)
#define SCC_GSMRL_ENR		((unsigned int)0x00000020)
#define SCC_GSMRL_ENT		((unsigned int)0x00000010)
#define SCC_GSMRL_MODE_ENET	((unsigned int)0x0000000c)
#define SCC_GSMRL_MODE_DDCMP	((unsigned int)0x00000009)
#define SCC_GSMRL_MODE_BISYNC	((unsigned int)0x00000008)
#define SCC_GSMRL_MODE_V14	((unsigned int)0x00000007)
#define SCC_GSMRL_MODE_AHDLC	((unsigned int)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS	((unsigned int)0x00000005)
#define SCC_GSMRL_MODE_UART	((unsigned int)0x00000004)
#define SCC_GSMRL_MODE_SS7	((unsigned int)0x00000003)
#define SCC_GSMRL_MODE_ATALK	((unsigned int)0x00000002)
#define SCC_GSMRL_MODE_HDLC	((unsigned int)0x00000000)

#define SCC_TODR_TOD		((unsigned short)0x8000)

/* SCC Event and Mask register.
*/
#define	SCCM_TXE	((unsigned char)0x10)
#define	SCCM_BSY	((unsigned char)0x04)
#define	SCCM_TX		((unsigned char)0x02)
#define	SCCM_RX		((unsigned char)0x01)

typedef struct scc_param {
	unsigned short	scc_rbase;	/* Rx Buffer descriptor base address */
	unsigned short	scc_tbase;	/* Tx Buffer descriptor base address */
	unsigned char	scc_rfcr;	/* Rx function code */
	unsigned char	scc_tfcr;	/* Tx function code */
	unsigned short	scc_mrblr;	/* Max receive buffer length */
	unsigned int	scc_rstate;	/* Internal */
	unsigned int	scc_idp;	/* Internal */
	unsigned short	scc_rbptr;	/* Internal */
	unsigned short	scc_ibc;	/* Internal */
	unsigned int	scc_rxtmp;	/* Internal */
	unsigned int	scc_tstate;	/* Internal */
	unsigned int	scc_tdp;	/* Internal */