imbx8xx.c

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*
 *  imbx8xx.c
 *
 *  MBX860/MBX821 initialization routines.
 *
 *  Copyright (c) 1999, National Research Council of Canada
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 */

#include <bsp.h>
#include <bsp/mbx.h>

/*
 *  EPPCBug rev 1.1 is stupid. It clears the interrupt mask register
 *  in the SIU when it takes control, but does not restore it before
 *  returning control to the program. We thus keep a copy of the
 *  register, and restore it from gdb using the hook facilities.
 *  
 *  We arrange for simask_copy to be initialized to zero so that
 *  it resides in the .data section. This avoids having gdb set
 *  the mask to crud before we get to initialize explicitly. Of
 *  course, the code will not be safely restartable, but then again,
 *  a lot of the library code isn't either, so there!
 */
unsigned32 simask_copy = 0;

/*
 *  The memory controller's UPMA Ram array values.
 *  The values in table 2-6 and 2-7 in the "MBX Series Embedded
 *  Controller Programmer's Reference Guide", part number MBXA/PG2,
 *  differ from the ones in the older MBX Programmer's Guide, part
 *  number MBXA/PG1. We are assuming that the values in MBXA/PG1
 *  are for the older MBX boards whose part number does not have
 *  the "B" suffix, but we have discovered that the values from
 *  MBXA/PG2 work better, even for the older boards. 
 *  
 *  THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and
 *  MBX860-002. USE WITH CARE!
 *  
 *  NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B
 *  as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz.
 *  We think the MBX821_001B is an entry level board and thus is 50 MHz,
 */
static unsigned32 upmaTable[64] = {

#if ( defined(mbx860_001b) || \
        defined(mbx821_001b) || \
        defined(mbx821_001) )

        /* 50 MHz MBX */
        /*
         * Note: For the mbx821_001, the following values (from the
         * MBXA/PG2 manual) work better than, but are different
         * from those published in the original MBXA/PG1 manual and
         * initialized by EPPCBug 1.1. In particular, the original
         * burst-write values do not work! Also, the following values
         * facilitate higher performance.
         */  
	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
	0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,

	/*  DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x00AF0C04,
	0x07AF0C08, 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08,
 	0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, 0x0CAF0C04,
	0x10AF0C04, 0xF0AFC000, 0xF3BF4805, 0xFFFFC005,

	/*  DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
	0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,

	/*  DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
	0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,

	/*  Refresh 60ns. (offset 0x30 in UPM RAM) */
	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
	0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
 
	/*  Exception. (offset 0x3c in UPM RAM) */
	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007

#elif ( defined(mbx860_002b) || \
        defined(mbx860_003b) || \
        defined(mbx860_004b) || \
        defined(mbx860_005b) || \
        defined(mbx860_006b) || \
        defined(mbx821_002b) || \
        defined(mbx821_003b) || \
        defined(mbx821_004b) || \
        defined(mbx821_005b) || \
        defined(mbx821_006b) || \
        defined(mbx860_001) || \
        defined(mbx860_002) || \
        defined(mbx860_003) || \
        defined(mbx860_004) || \
        defined(mbx860_005) || \
        defined(mbx821_002) || \
        defined(mbx821_003) || \
        defined(mbx821_004) || \
        defined(mbx821_005) )

        /* 40 MHz MBX */
        /*
         * Note: For the older MBX models (i.e. without the "b" 
         * suffix, e.g. mbx860_001), the following values (from the
         * MBXA/PG2 manual) work better than, but are different
         * from those published in the original MBXA/PG1 manual and
         * initialized by EPPCBug 1.1. In particular, the following
         * burst-read and burst-write values facilitate higher
         * performance.
         */  
	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
	0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,

	/*  DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
	0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
 	0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,

	/*  DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
	0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x33FF4804,
	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,

	/*  DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
	0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x03FF0C0C,
	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
	0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,

	/*  Refresh 60ns. (offset 0x30 in UPM RAM) */
	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
	0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
 
	/*  Exception. (offset 0x3c in UPM RAM) */
	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
#else
#error "MBX board model not specified."
#endif
};

/*
 *  Initialize MBX8xx
 */
void _InitMBX8xx (void)
{
  register unsigned32 r1, i;
  extern unsigned32 simask_copy;

  /*			
   *  Initialize the Debug Enable Register (DER) to an appropriate
   *  value for EPPCBug debugging. 
   *  (This value should also work for BDM debugging.)
   */
  r1 = 0x70C67C07;	/* All except EXTIE, ALIE, DECIE */
  _mtspr( M8xx_DER, r1 );
  
  /*
   * Initialize the Instruction Support Control Register (ICTRL) to a
   * an appropriate value for normal operation. A different value,
   * such as 0x0, may be more appropriate for debugging.
   */
  r1 = 0x00000007;
  _mtspr( M8xx_ICTRL, r1 );
	
  /*
   * Disable and invalidate the instruction and data caches.
   */
  r1 = M8xx_CACHE_CMD_DISABLE;
  _mtspr( M8xx_IC_CST, r1 );
  _isync;
  r1 = M8xx_CACHE_CMD_UNLOCKALL;
  _mtspr( M8xx_IC_CST, r1 );
  _isync;
  r1 = M8xx_CACHE_CMD_INVALIDATE;	/* invalidate all */
  _mtspr( M8xx_IC_CST, r1 );
  _isync;
  
  r1 = M8xx_CACHE_CMD_DISABLE;
  _mtspr( M8xx_DC_CST, r1 );
  _isync;
  r1 = M8xx_CACHE_CMD_UNLOCKALL;
  _mtspr( M8xx_DC_CST, r1 );
  _isync;
  r1 = M8xx_CACHE_CMD_INVALIDATE;	/* invalidate all */
  _mtspr( M8xx_DC_CST, r1 );
  _isync;

  /*
   *  Initialize the Internal Memory Map Register (IMMR)
   *
   *  Use the value in MBXA/PG2, which is also the value that EPPC-Bug
   *  programmed into our boards. The alternative is the value in
   *  MBXA/PG1: 0xFFA00000. This value might well depend on the revision
   *  of the firmware.
   *
   *  THIS VALUE IS ALSO DECLARED IN THE linkcmds FILE and mmutlbtab.c!
   */
  r1 = 0xFA200000;
  _mtspr( M8xx_IMMR, r1 );

  /*
   *  Get the SIU interrupt mask.
   *  imd: accessing m8xx.* should not occure before setting up the immr !
   */
   simask_copy = m8xx.simask;
  
  /* 
   * Initialize the SIU Module Configuration Register (SIUMCR) 
   * m8xx.siumcr = 0x00602900, the default MBX and firmware value.
   */
  m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | 
		M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME;
  
  /*
   * Initialize the System Protection Control Register (SYPCR).
   * The SYPCR can only be written once after Reset.
   *	- Enable bus monitor
   *	- Disable software watchdog timer
   * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value.
   */
  m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | 
		M8xx_SYPCR_BME | M8xx_SYPCR_SWF;

  /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */
  m8xx.siel = 0xAAAA0000;         	/* Default MBX and firmware value. */
  
  /* Initialize the Transfer Error Status Register (TESR) */
  m8xx.tesr = 0xFFFFFFFF;         	/* Default firmware value. */
  
  /* Initialize the SDMA Configuration Register (SDCR) */
  m8xx.sdcr = 0x00000001;         	/* Default firmware value. */
  
  /*
   * Initialize the Timebase Status and Control Register (TBSCR)
   * m8xx.tbscr = 0x00C3, default MBX and firmware value.
   */
  m8xx.tbscrk = M8xx_UNLOCK_KEY;	/* unlock TBSCR */
  m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | 
  		M8xx_TBSCR_TBF | M8xx_TBSCR_TBE;
  
  /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */
  m8xx.rtcsk = M8xx_UNLOCK_KEY;		/* unlock RTCSC */
  m8xx.rtcsc = 0x00C3;			/* Default MBX and firmware value. */
  
  /* Unlock other Real-Time Clock registers */
  m8xx.rtck = M8xx_UNLOCK_KEY;		/* unlock RTC */
  m8xx.rtseck = M8xx_UNLOCK_KEY;	/* unlock RTSEC */
  m8xx.rtcalk = M8xx_UNLOCK_KEY;	/* unlock RTCAL */
  
  /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
  m8xx.piscrk = M8xx_UNLOCK_KEY;	/* unlock PISCR */
  m8xx.piscr = 0x0083; 			/* Default MBX and firmware value. */
      
  /* Initialize the System Clock and Reset Control Register (SCCR)
   * Set the clock sources and division factors:
   *   Timebase Source is GCLK2 / 16
   *   Real-Time Clock Select is EXTCLK (4.192MHz)
   *   Real-Time Clock Divide is /4
   */
  m8xx.sccrk = M8xx_UNLOCK_KEY;		/* unlock SCCR */
  m8xx.sccr = 0x02800000;		/* for MBX860/MBX821 */

#if 0 /* IMD hack: do not init PLL after EPPCbug load */
  /* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */
  /* - set the clock speed and set normal power mode */
  m8xx.plprck = M8xx_UNLOCK_KEY;	/* unlock PLPRCR */
#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
  m8xx.plprcr = 0x5F500000;
#elif ( defined(mbx860_005b) || \
        defined(mbx860_002b) || \
        defined(mbx860_003b) || \
        defined(mbx860_004b) || \
        defined(mbx860_006b) || \
        defined(mbx821_002b) || \
        defined(mbx821_003b) || \
        defined(mbx821_004b) || \
        defined(mbx821_005b) || \
        defined(mbx821_006b) )
  /* Set the multiplication factor to 0 and clear the timer interrupt status*/
  m8xx.plprcr = 0x00005000;
#elif ( defined(mbx860_001) || \
        defined(mbx860_002) || \
        defined(mbx860_003) || \
        defined(mbx860_004) || \
        defined(mbx860_005) || \
        defined(mbx821_002) || \
        defined(mbx821_003) || \
        defined(mbx821_004) || \
        defined(mbx821_005))
  m8xx.plprcr = 0x4C400000;
#else
#error "MBX board not defined"  
#endif
#endif
  /* Unlock the timebase and decrementer registers. */
  m8xx.tbk = M8xx_UNLOCK_KEY;
  /* 
   * Initialize decrementer register to a large value to
   * guarantee that a decrementer interrupt will not be
   * generated before the kernel is fully initialized.
   */
  r1 = 0x7FFFFFFF;
  _mtspr( M8xx_DEC, r1 );
	
  /* Initialize the timebase register (TB is 64 bits) */
  r1 = 0x00000000;
  _mtspr( M8xx_TBU_WR, r1 );
  _mtspr( M8xx_TBL_WR, r1 );