📄 align_h.s
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.long stwx /* b 1B 0x097 */ .long stwux /* b 1C 0x0B7 */ .long 0 /* b 1D */ .long 0 /* b 1E */ .long lhzx /* b 1F 0x117 *//* * for all handlers * r4 - Addressability to interrupt context * r5 - DEAR address (faulting data address) * r6 - RA field * 4 * r7 - Address of GPR 0 in image * r8 - RD field * 4 * r9 - Failing instruction *//* Load halfword algebraic with update */lhau:/* Load halfword algebraic with update indexed */lhaux: stwx r5,r7,r6 /* update RA with effective addr *//* Load halfword algebraic */lha:/* Load halfword algebraic indexed */lhax: lswi r10,r5,2 /* load two bytes into r10 */ srawi r10,r10,16 /* shift right 2 bytes, extending sign */ stwx r10,r7,r8 /* update reg image */ b align_complete /* return *//* Load Half Word Byte-Reversed Indexed */lhbrx: lswi r10,r5,2 /* load two bytes from DEAR into r10 */ rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */ stwbrx r10,r7,r8 /* store reversed in reg image */ b align_complete /* return *//* Load Half Word and Zero with Update */lhzu:/* Load Half Word and Zero with Update Indexed */lhzux: stwx r5,r7,r6 /* update RA with effective addr *//* Load Half Word and Zero */lhz:/* Load Half Word and Zero Indexed */lhzx: lswi r10,r5,2 /* load two bytes from DEAR into r10 */ rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */ stwx r10,r7,r8 /* update reg image */ b align_complete /* return *//* * Load Multiple Word */lmw: lwzx r9,r6,r7 /* R9 contains saved value of RA */ addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ subfic r8,r8,32 /* r8 is reg count to load */ mtctr r8 /* load counter */ addi r8,r8,-1 /* r8-- */ rlwinm r8,r8,2,2,31 /* r8 *= 4 */ add r5,r5,r8 /* update DEAR to point to last reg */lwmloop: lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */ stwu r11,-4(r10) /* load image and decrement pointer */ addi r5,r5,-4 /* decrement effective address */ bdnz lwmloop stwx r9,r6,r7 /* restore RA (in case it was trashed) */ b align_complete /* return *//* * Load Word and Reserve Indexed */lwarx: lswi r10,r5,4 /* load four bytes from DEAR into r10 */ stwx r10,r7,r8 /* update reg image */ rlwinm r5,r5,0,0,29 /* Word align address */ lwarx r10,0,r5 /* Set reservation */ b align_complete /* return *//* * Load Word Byte-Reversed Indexed */lwbrx: lswi r10,r5,4 /* load four bytes from DEAR into r10 */ stwbrx r10,r7,r8 /* store reversed in reg image */ b align_complete /* return *//* Load Word and Zero with Update */lwzu:/* Load Word and Zero with Update Indexed */lwzux: stwx r5,r7,r6 /* update RA with effective addr *//* Load Word and Zero */lwz:/* Load Word and Zero Indexed */lwzx: lswi r10,r5,4 /* load four bytes from DEAR into r10 */ stwx r10,r7,r8 /* update reg image */ b align_complete /* return *//* Store instructions *//* *//* Store Half Word and Update */sthu:/* Store Half Word and Update Indexed */sthux: stwx r5,r7,r6 /* Update RA with effective address *//* Store Half Word */sth:/* Store Half Word Indexed */sthx: lwzx r10,r8,r7 /* retrieve source register value */ rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */ stswi r10,r5,2 /* store bytes to DEAR address */ b align_complete /* return *//* *//* Store Half Word Byte-Reversed Indexed */sthbrx: lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ stswi r10,r5,2 /* move two bytes to DEAR address */ b align_complete /* return *//* *//* Store Multiple Word */stmw: addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ subfic r8,r8,32 /* r8 is reg count to load */ mtctr r8 /* load counter */ addi r8,r8,-1 /* r8-- */ rlwinm r8,r8,2,2,31 /* r8 *= 4 */ add r5,r5,r8 /* update DEAR to point to last reg */stmloop: lwzu r11,-4(r10) /* get register value */ stswi r11,r5,4 /* output to DEAR address */ addi r5,r5,-4 /* decrement effective address */ bdnz stmloop b align_complete /* return *//* *//* Store Word and Update */stwu:/* Store Word and Update Indexed */stwux: stwx r5,r7,r6 /* Update RA with effective address *//* Store Word */stw:/* Store Word Indexed */stwx: lwzx r10,r8,r7 /* retrieve source register value */ stswi r10,r5,4 /* store bytes to DEAR address */ b align_complete /* return *//* *//* Store Word Byte-Reversed Indexed */stwbrx: lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ stswi r10,r5,4 /* move two bytes to DEAR address */ b align_complete /* return *//* *//* Store Word Conditional Indexed */stwcx: rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */ lwz r11,0(r10) /* save original value of store */ stwcx. r11,r0,r10 /* attempt store to address */ bne stwcx_moveon /* store failed, move on */ stw r11,0(r10) /* repair damage */ lwzx r9,r7,r8 /* get register value */ stswi r10,r5,4 /* store bytes to DEAR address */stwcx_moveon: mfcr r11 /* get condition reg */ lwz r9,Open_cr(r1) /* get condition reg image */ rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */ lwz r11,Open_xer(r1) /* get XER reg */ rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */ stw r9,Open_cr(r1) /* store cr image */ b align_complete /* return *//* *//* Data Cache Block Zero */dcbz: rlwinm r5,r5,0,0,31-CACHE_SIZE_L2 /* get address to nearest Cache line */ addi r5,r5,-4 /* adjust by a word */ addi r10,r0,CACHE_SIZE/4 /* set counter value */ mtctr r10 addi r11,r0,0 /* r11 = 0 */dcbz_loop: stwu r11,4(r5) /* store a word and update EA */ bdnz dcbz_loop b align_complete /* return */align_complete: /*----------------------------------------------------------------------- * Restore regs and return from the interrupt *----------------------------------------------------------------------*/ lmw r24,Open_xer+ALIGN_REGS(r0) mtxer r24 mtlr r25 mtctr r26 mtcrf 0xFF, r27#if defined(ppc403) || defined(ppc405) mtspr srr2, r28 /* SRR 2 */ mtspr srr3, r29 /* SRR 3 */#endif mtspr srr0, r30 /* SRR 0 */ mtspr srr1, r31 /* SRR 1 */ lmw r1,Open_gpr1+ALIGN_REGS(r0) lwz r0,Open_gpr0+ALIGN_REGS(r0) rfi⌨️ 快捷键说明
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