registers.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/* KEYROW register                                                            */
#define MSK_ROW         0x1F                /* mask on ROW field              */
#define KEYRELEASE      0x80

/* CLKCNTL register                                                           */
#define MOSCDISABLE     0x02
#define OVERSAM         0x04
#define SQUARER         0x08
#define SWRESET         0x80
#define SWFLAG          0x80
#define TSTN_DISABLE    0x40
#define MODE55          0x10

/** THUMB and INTERFACES BLOCK                                                */

/* CSCNTL0[6:0] registers                                                     */
#define MSK_SETUP       0x0007
#define SETUP_RD        0x0040
#define SETUP_HZ        0x0080
#define MSK_WIDTH       0x1F00
#define MSK_HZWS        0xE000

/* CSCNTL1[6:0] registers                                                     */
#define MSK_CSMODE      0x0003
#define MSK_HOLD        0x0070
#define HOLD_RD         0x0080
#define MSK_WIDTH_WR    0x0700
#define USE_WIDTH_WR    0x4000
#define WR_SHIFED       0x8000

#define CSMODE_8        0x0000
#define CSMODE_16_WHWL  0x0002
#define CSMODE_16_BHBL  0x0003


/* MUXADCNTL register                                                         */
#define MSK_AHOLD       0x0007
#define MSK_ALEWIDTH    0x0070

/* PORTCNTL register                                                          */
#define CS0_             0x0001
#define CS1_             0x0002
#define CS2_             0x0004
#define CS3_             0x0008
#define CS4_             0x0010
#define CS5_             0x0020
#define CS6_             0x0040
#define DATA_H          0x0080
#define INT0            0x0100
#define INT1            0x0200
#define INT2            0x0400
#define INT3            0x0800
#define MSK_ADDRESS     0x7000
#define EXTMEM          0x8000

#define ADDRESS_128K    0x0000
#define ADDRESS_256K    0x1000
#define ADDRESS_512K    0x2000
#define ADDRESS_1M      0x3000
#define ADDRESS_2M      0x4000


/* CSGCNTL register                                                           */
#define CSSWITCH        0x0040


/* SLEEPCNTL register                                                         */
#define EXPIRED         0x01
#define SLEEP_ENABLE    0x80

/* WDCNTL register                                                            */
#define WDSTROKE        0x80
#define WDFLAG          0x80                /* same bit                       */


/* DCC register                                                               */
/* bit ENABLE=0x80 already defined */ 
#define DCC_ENABLE   0x80


/* TIMERCNTL[0:1] register                                                    */
/* bit ENABLE=0x80 already defined */ 
#define TIMER_ENABLE   0x80
#define RELOAD          0x0040
#define MSK_FREQ        0x0003              /* mask on FREQ field             */
#define TIMER_13824kHz  0x0003
#define TIMER_864kHz    0x0002
#define TIMER_216kHz    0x0001
#define TIMER_27kHz     0x0000


/* INTMASKALL register                                                        */
#define MASKIRQ         0x80
#define MASKFIQ         0x40

/* INTEOI register                                                            */
#define EOI             0x80

/* INTMASK register                                                           */
/* INTSTAT register                                                           */
/* INTIS register                                                             */

#define PLP             0x0001
#define PCM             0x0002
#define SRX             0x0004
#define STX             0x0008
#define TMR0            0x0010
#define TMR1            0x0020
#define LCDEE           0x0100
#define KPAD            0x0200
#define TAD             0x0400
#define ADC             0x0800
#define EXT0            0x1000
#define EXT1            0x2000
#define EXT2            0x4000
#define EXT3            0x8000

/* INTCNTL[0:15] register                                                     */
#define MSK_PRIO        0x0007
#define RE              0x0008
#define RISING          0x0040
#define EDGE            0x0080

/* INTHPAI register                                                           */
#define AUTOACK         0x0080


/******************************************************************************
 * Memory Mapping definition 
 ******************************************************************************
 */

#define CSN0_BASE_ADR   0x00200000          /* Base Address of CSN0           */
#define CSN1_BASE_ADR   0x00400000          /* Base Address of CSN1           */
#define CSN2_BASE_ADR   0x00600000          /* Base Address of CSN2           */
#define CSN3_BASE_ADR   0x00800000          /* Base Address of CSN3           */
#define CSN4_BASE_ADR   0x00A00000          /* Base Address of CSN4           */
#define CSN5_BASE_ADR   0x00C00000          /* Base Address of CSN5           */
#define CSN6_BASE_ADR   0x00E00000          /* Base Address of CSN6           */

#define IRAM_BASE_ADR   0x00000000          /* Base Addr. of int. Data Memory */
#define SHRAM_BASE_ADR  0x00080000          /* Base Address of Share Memory   */
#define REGS_BASE_ADR   0x000F0000          /* Base Address of registers      */
#define RADRAM_BASE_ADR 0x000F0000          /* Base Address of registers      */


/******************************************************************************
 * Slot Control bloc 
 ******************************************************************************
 */

#ifndef __asm__
/*** Slot Control Block structure                                           ***/
typedef volatile struct                     /* normal Slot Control Block      */
{
    unsigned char RAD0;
    unsigned char RAD1;
    unsigned char MODE;
    unsigned char CNTL0;
    unsigned char CNTL1;
    unsigned char CNTL2;
    unsigned char STAT0;                       
    unsigned char STAT1;
    unsigned char STAT2;
    unsigned char CRYPT;
    unsigned char MUTE;
    unsigned char INT_;
    unsigned char AMSG;
    unsigned char AHDR;
    unsigned short APTR;
    unsigned short IPTR;
    unsigned short CfPTR;
    unsigned short OtPTR;
    unsigned char OFFCNTL;
    unsigned char WINCNTL;
} LM_SCB;

typedef LM_SCB *LM_SCB_P;                   /* pointer to Slot Control Block  */
#endif

/*** BIT MASKS for Slot Control Block parameters                            ***/

/* RAD0 parameter                                                             */
#define RC_RSSIENB  0x80                    /* RSSI measurement control       */
#define RC_ANTENNA2 0x08                    /* antenna[2] selection           */
#define RC_ANTENNA1 0x04                    /* antenna[1] selection           */
#define RC_ANTENNA0 0x02                    /* antenna[0] selection           */
#define RC_SYNOUT   0x01                    /* synthesiser selection          */

#define RC_ANTSEL   0x0E                    /* mask on RC antenna selection   */

/* RAD1 parameter                                                             */
#define RC_RFC      0xF0                    /* mask on RC RF carrier number   */
#define RC_RFSCAN   0x08                    /* RF carrier source selection    */
#define RC_SYNLATCH 0x04                    /* synthesizer #n Latch Enabled   */
#define RC_SYN_TX   0x03                    /* slot is TX (synthesizer data)  */
#define RC_SYN_RX   0x02                    /* slot is RX (synthesizer data)  */

#define RC_SYNSLOT  0x03                    /* mask on Synthesizer slot type  */

/* MODE parameter                                                             */
#define AUTOB1      0x80
#define AUTOB0      0x40
#define P00         0x20

#define MSK_MODE    0x1F                    /* mask on SCB MODE field         */

/* CNTL0 parameter                                                            */
#define LU7CH       0x80

#define MSK_BOFF    0x7F                    /* mask on BOFF field             */

/* CNTL1 parameter                                                            */
#define TX          0x80
#define RESYNC      0x40
#define Q1          0x40                    /* Q1/RESYNC mapped on same bit   */
#define INHBST      0x20
#define Q2          0x20                    /* Q2/INHBST mapped on same bit   */
#define CTPACK      0x10

#define MSK_CTFLEN  0x0F                    /* mask on CTFLEN field           */

/* CNTL2 parameter                                                            */
#define SLTEN       0x80
#define SINV        0x40
#define ALL         0x20
#define CO_CL       0x20                   /* CO_CL/ALL mapped on same bit    */
#define INTEN       0x10
#define SCOR1       0x08
#define SCOR0       0x04
#define BINTE       0x02
#define BINTU       0x01

#define MSK_SCOR    0x0C                    /* mask on SCOR field             */

/* STAT0 parameter                                                            */
#define ZFAIL0      0x80
#define ZFAIL1      0x40
#define ZFAIL2      0x20
#define ZFAIL3      0x10
#define SCRD1       0x08
#define SCRD0       0x04
#define PRED1       0x02
#define PRED0       0x01

#define MSK_ZFAIL   0xF0                    /* mask on ZFAIL field            */
#define MSK_SCRD    0x0C                    /* mask on SCRD field             */
#define MSK_PRED    0x03                    /* mask on PRED field             */

/* STAT1 parameter                                                            */
#define BCRC7       0x80
#define BCRC6       0x40
#define BCRC5       0x20
#define BCRC4       0x10
#define BCRC3       0x08
#define BCRC2       0x04
#define BCRC1       0x02
#define BCRC0       0x01

/* STAT2 parameter                                                            */
#define TMUX        0x80
#define RADIO       0x40
#define RFPI        0x20
#define XCRC        0x10
#define ACRC        0x08
#define SYNC        0x04
#define BCRC        0x02
#define BCRC8       0x01

/* CRYPT parameter                                                            */
#define LONG        0x80
#define INIP        0x40
#define ACRYPT      0x20
#define BCRYPT      0x10

#define MSK_EETBL   0x0F                    /* mask on EETBL field            */

/* MUTE  parameter                                                            */
#define NOTI        0x80
#define XFAIL       0x40
#define AFAIL       0x20
#define NOSYNC      0x10                    /*NOSYNC/TXMUTE mapped on same bit*/
#define TXMUTE      0x10

#define MSK_CHAN    0x0F                    /* mask on CHAN field             */

/* INT   parameter                                                            */
/* Bit RADIO is already defined                                               */
#define Q1Q2        0x80
#define RFP_I       0x20
#define X_CRC       0x10
#define R_CRC       0x08
#define SYNCFAIL    0x04
#define ASYNCOK     0x02
#define ZFIELD      0x01

/* AMSG  parameter                                                            */
#define PP_FP       0x80   
#define CT          0x40
#define NT          0x20                    /* NT/CTSEND mapped on same bit   */
#define CTSEND      0x20
#define MTFIRST     0x10                    /* MTFIRST/QT mapped on same bit  */
#define QT          0x10
#define MT          0x08
#define MTWAIT      0x04
#define PT          0x02
#define ESCAPE      0x01

/* WINCNTL  parameter                                                         */
#define LM_WIN_NONE 0x00                    /* no sync window                 */
#define LM_WIN_OPEN 0x3F                    /* wide open window size          */
#define MSK_WINSZ   0x3F





/* 
 * Some macros to mask the VEGA+ interrupt sources                            
 ******************************************************************************
 */

#define LM_MaskPLP()           (LM_Regs[INTMASK] |= PLP)
#define LM_MaskPCM()           (LM_Regs[INTMASK] |= PCM)

/* Vega+ product version */
#define LM_MaskUART()          (LM_Regs[INTMASK] |= SRX)
#define LM_MaskSRX()           (LM_Regs[RSIER]   &= ~RX_INT_ENABLE)
#define LM_MaskSTX()           (LM_Regs[RSIER]   &= ~TX_INT_ENABLE)
#define LM_MaskUARTStatus()    (LM_Regs[RSIER]   &= ~LINE_STATUS_ENABLE)


#define LM_MaskTMR0()          (LM_Regs[INTMASK] |= TMR0)
#define LM_MaskTMR1()          (LM_Regs[INTMASK] |= TMR1)
#define LM_MaskLCDEE()         (LM_Regs[INTMASK] |= LCDEE)
#define LM_MaskKPAD()          (LM_Regs[INTMASK] |= KPAD)
#define LM_MaskTAD()           (LM_Regs[INTMASK] |= TAD)
#define LM_MaskADC()           (LM_Regs[INTMASK] |= ADC)
#define LM_MaskEXT0()          (LM_Regs[INTMASK] |= EXT0)
#define LM_MaskEXT1()          (LM_Regs[INTMASK] |= EXT1)
#define LM_MaskEXT2()          (LM_Regs[INTMASK] |= EXT2)
#define LM_MaskEXT3()          (LM_Regs[INTMASK] |= EXT3)

/* Some macros to ummask the VEGA+ interrupt sources                          */
#define LM_UnMaskPLP()         (LM_Regs[INTMASK] &= ~PLP)
#define LM_UnMaskPCM()         (LM_Regs[INTMASK] &= ~PCM)

/* Vega+ product version */
#define LM_UnMaskUART()        (LM_Regs[INTMASK] &= ~SRX)
#define LM_UnMaskSRX()         (LM_Regs[RSIER]   |= RX_INT_ENABLE)
#define LM_UnMaskSTX()         (LM_Regs[RSIER]   |= TX_INT_ENABLE)
#define LM_UnMaskUARTStatus()  (LM_Regs[RSIER]   |= LINE_STATUS_ENABLE)

#define LM_UnMaskTMR0()        (LM_Regs[INTMASK] &= ~TMR0)
#define LM_UnMaskTMR1()        (LM_Regs[INTMASK] &= ~TMR1)
#define LM_UnMaskLCDEE()       (LM_Regs[INTMASK] &= ~LCDEE)
#define LM_UnMaskKPAD()        (LM_Regs[INTMASK] &= ~KPAD)
#define LM_UnMaskTAD()         (LM_Regs[INTMASK] &= ~TAD)
#define LM_UnMaskADC()         (LM_Regs[INTMASK] &= ~ADC)
#define LM_UnMaskEXT0()        (LM_Regs[INTMASK] &= ~EXT0)
#define LM_UnMaskEXT1()        (LM_Regs[INTMASK] &= ~EXT1)
#define LM_UnMaskEXT2()        (LM_Regs[INTMASK] &= ~EXT2)
#define LM_UnMaskEXT3()        (LM_Regs[INTMASK] &= ~EXT3)

/* Some macros to Acknoledge the VEGA+ interrupt sources                      */
#define LM_AckPLP()            (LM_Regs[INTACK] |= PLP)
#define LM_AckPCM()            (LM_Regs[INTACK] |= PCM)
#define LM_AckTMR0()           (LM_Regs[INTACK] |= TMR0)
#define LM_AckTMR1()           (LM_Regs[INTACK] |= TMR1)
#define LM_AckEXT0()           (LM_Regs[INTACK] |= EXT0)
#define LM_AckEXT1()           (LM_Regs[INTACK] |= EXT1)
#define LM_AckEXT2()           (LM_Regs[INTACK] |= EXT2)
#define LM_AckEXT3()           (LM_Regs[INTACK] |= EXT3)

/*#define INIT_LMREGS_MAPPING()	{ LM_Regs = (unsigned long*)REGS_BASE_ADR; }*/

#endif /*__LMREGS_H__*/