registers.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/* RCIOCNTL1 register                                                         */
#define MSK_GPO         0x0F                /* Mask on GPO field              */
#define P00ENB          0x10
#define ABORT           0x20
#define TXIO            0x40
#define TXINV           0x80

/* RCIOCNTL2 register                                                         */
#define SELRFCLK        0x01
#define SELRXPWR        0x02
#define TXPWRINV        0x04
#define RXPWRINV        0x08
#define SYNTHPWR0INV    0x10
#define SYNTHPWR1INV    0x20
#define TXDRONINV       0x40
#define SELTXDRON       0x80

/* RCIOCNTL3 register                                                         */
#define D2SMODE         0x01
#define DRCNTL          0x02
#define MSK_SELGPO      0x0C                /* Mask on SELGPO field           */
#define MSK_SUSPANT     0x30                /* Mask on SUSO/ANT field         */

/* SHAPERCNTL register                                                        */
#define INV             0x01
#define MID             0x02
#define PWRDWN          0x04
#define DACENB          0x80

/* SYNTFCNTL register                                                         */
#define SYNT_FREQ       0x80

/* SYNTCNTL0 register                                                         */
#define PWRFREQ         0x01
#define CLKPHASE        0x08
#define LETYPE          0x10
#define RPIPEON         0x20
#define PWRSGN          0x40
#define OUTLOCK         0x80

/* SYNTCNTL1 register                                                         */
#define SLE0            0x01
#define SLE1            0x02
#define SLE2            0x04
#define LEMODE          0x08
#define LESEL           0x10
#define SCLK            0x20
#define SDATA           0x40
#define HPMODE_SYNT     0x80

/* SYNTCNTL2 register                                                         */
#define START_DONE      0x80
#define MSK_N           0x03                /* Mask on N field                */

/* SYNTCNTL3 register                                                         */
#define RXPWRDNSEN      0x01
#define RXPWRUNSEN      0x02
#define TXPWRDNSEN      0x04
#define TXPWRUNSEN      0x08
#define SEQCNTL         0x10
#define ALIGN           0x20
#define PLLWORD         0x40
#define PRESEQ          0x80

/* RFSCAN register                                                            */
#define MSK_RF          0x0F                /* Mask on RF field               */
#define RFMAX           0x80

/* RSSIRANGE register                                                         */
#define MSK_VREFP       0x03                /* Mask on VREFP field            */
#define MSK_VREFN       0x0C                /* Mask on VREFN field            */

/* RSSICNTL register                                                          */
#define MSK_MODE_RSSI   0x03                /* Mask on MODE field             */
#define MARKFF          0x04
#define TXMARK          0x08
#define ALL_RSSI        0x10
#define RSSIACT         0x20
#define RSSIDIS         0x40
#define RSSIENB         0x80

/* RCCNTL register                                                            */
#define RCCNTL_ENABLE   0x80


/* ADCCNTL1 register                                                          */
#define ADCSTART        0x80
#define SCAN            0x40
#define ADCENB          0x80
#define MSK_ADCSEL      0x07

/* ADCCNTL2 register                                                          */
#define ADCOVER1        0x01
#define ADCOVER2        0x02
#define ADCDWN1         0x04
#define ADCDWN2         0x08



/** PLP BLOCK                                                                 */

/* DCNTL0 register                                                            */
#define TMUXINT         0x01
#define MUTEIP          0x02
#define Q1Q2_PLP        0x04
#define TRANSP          0x08
#define CRYPTALL        0x10
#define TXSENSE         0x20
#define ZACT            0x40
#define PLPENB          0x80

/* DCNTL1 register                                                            */
#define ONECT           0x10
#define WOMODE          0x40
#define WOENB           0x80
#define MSK_RPIPE       0x07                /* mask on RPIPE field            */

/* RXSYNCT register                                                           */
#define PRSIZE          0x04
#define PREEN           0x08
#define PRETYPE         0x40
#define PROLONG         0x80

#define MSK_SYCNT       0x30                /* mask on SYCNT field            */
#define MSK_PTHR        0x03                /* mask on PTHR field             */

/* CLOCK_CORR register                                                        */
#define SIGN            0x80

/* PRESYNC register                                                           */
#define PRESENB         0x80

#define MSK_PRES        0x0F                /* mask on PRES field             */


/* PLPALIN register                                                           */
#define SYNM            0x08
#define BITSLIP         0x10
#define SLOTFAIL        0x20
#define DFFAIL          0x40
#define LONGDF          0x80
#define MODE_PLPALIN    0x03                /* mask on PLP alignment mode     */

/* SUSPCNTL register                                                          */
#define SUSPENB         0x01

/* TSTCNTL register                                                           */
#define DISBSCR         0x01
#define TX_TST          0x02
#define DATADIR         0x04

/* TSTDST register                                                            */
#define RDY             0x80

/** ENCRYPTION ENGINE                                                         */

/* EECNTL register                                                            */
/* Bit ENABLE already defined                                                 */
#define EECNTL_ENABLE   0x80


/** PAINT+ BLOCK                                                              */

/* PAINTCNTL register                                                         */
#define MUTEDIS0        0x0001
#define MUTEDIS1        0x0002
#define MEMLOOP0        0x0004
#define MEMLOOP1        0x0008
#define RATE0           0x0010
#define RATE1           0x0020
#define CHAN0ENB        0x0040
#define CHAN1ENB        0x0080
#define BG0ENABLE       0x0100
#define BG1ENABLE       0x0200
#define PADENABLE       0x2000
#define FORCE13         0x4000
#define PAINTENB        0x8000


/* PAINTPLLCNTL register                                                      */
#define MSK_MC          0x001F              /* Mask on MC field               */
#define MCSIGN          0x0020
#define MANUAL          0x0080
#define RANG0           0x0100
#define RANG1           0x0200
#define RANG2           0x0400
#define MSK_RANG        0x0700              /* Mask on RANG field             */
#define FREEZD          0x1000
#define FREEZP          0x2000
#define PPFP            0x8000

/* PAINTPLLSTAT register                                                      */
#define MSK_DPHI        0x01FF              /* Mask on DPHI field             */
#define LOCKD           0x1000
#define LOCKP           0x2000
#define NOSIG           0x8000

/* HPPCMCNTL register                                                         */
#define LEN0            0x0001
#define LEN1            0x0002
#define LEN2            0x0004
#define MSK_LEN         0x0007              /* Mask on LEN field              */
#define FREQ0           0x0010
#define FREQ1           0x0020
#define MSK_PCMFREQ     0x0030              /* Mask on FREQ field             */
#define FSTYP0          0x0100
#define FSTYP1          0x0200
#define MSK_FSTYP       0x0300              /* Mask on FSTYP field            */
#define IOD0            0x0400
#define IOD1            0x0800
#define MSK_IOD         0x0C00              /* Mask on FSTYP field            */
#define IOCK            0x1000
#define MASTER          0x4000
#define PCMENB          0x8000

/* VBAFECNTL register                                                         */
#define MSK_VOLMIC      0x0007              /* Mask on VOLMIV field           */
#define MICDIF          0x0010
#define ENBMICREF       0x0080
#define MODE0           0x0100
#define MODE1           0x0200
#define MODE2           0x0400
#define LOOP0           0x1000
#define LOOP1           0x2000
#define FLOAT           0x4000
#define VBAFENB         0x8000

/* VBAFEAMP register                                                          */
#define MSK_VOL1OUT     0x000F              /* Mask on VOL1OUT field          */
#define ENBCH1          0x0010
#define MSK_VOL2OUT     0x0F00              /* Mask on VOL2OUT field          */
#define ENBCH2          0x1000

/* VBAFEPREAMP register                                                       */
#define MSK_VOLIN       0x000F              /* Mask on VOLIN field            */
#define MSK_ATT         0x0070              /* Mask on ATT field              */
#define PRCNF0          0x0100
#define PRCNF1          0x0200
#define PRCNF2          0x0400

/* MPDCNTL register                                                           */
#define MPD_FREQ        0x0001
#define MPD_ENB         0x0080

/* MPDREADY register                                                          */
#define MPD_RDY         0x0001

/* G726CNTL0 register                                                         */
#define RXTONE0         0x0001
#define RXTONE1         0x0002
#define TXTONE0         0x0004
#define TXTONE1         0x0008
#define SCALE0          0x0010
#define SCALE1          0x0020
#define MSK_SCALE       0x0030              /* Mask on SCALE field            */

/* G726CNTL1 register                                                         */
#define LAW             0x0001
#define UPCM            0x0002
#define G726_TXMUTE     0x0004
#define G726_RXMUTE     0x0008
#define SIDETONE        0x0010
#define SCA             0x0020
#define G726ENB         0x0080

/* G726CHANNEL register                                                       */
#define CHAN            0x0002

/* G726CHANENB register                                                       */
#define G726ENB0        0x0001
#define G726ENB1        0x0003


/** GENERAL REGISTERS BLOCK                                                   */

/* RINGCNTL register                                                          */
/* Bit ENABLE already defined                                                 */
#define RINGCNTL_ENABLE   0x80
#define FULL_BRIDGE     0x40
#define MSK_DELAY       0x30
#define RING_PADENB     0x08
#define MSK_LEVEL       0x07                /* mask on LEVEL field            */

/* RSIER register   (UART Interrupt enable register definition)               */
#define		LINE_STATUS_ENABLE	0x04
#define		TX_INT_ENABLE			0x02
#define		RX_INT_ENABLE			0x01

/* RSIIR register   (UART Interrupt identification register definition)       */
#define		FIFO_ENABLE_MASK		0xC0
#define		INT_ID_MASK				0x0E
#define		PENDING_INT_FLAG		0x01
#define		LINE_STATUS_INT		0x06 /* values for interrupt identification  */
#define		RX_INT					0x04
#define		FIFO_TIMEOUT_INT		0x0C
#define		TX_EMPTY_INT			0x02

/* RSFCR register   (UART Tx/Rx FIFO control register definition)             */
#define		RX_LEVEL_MASK			0xC0
#define		CLEAR_TX_FIFO			0x04
#define		CLEAR_RX_FIFO			0x02
#define		FIFO_ENABLE				0x01
#define		_1_BYTE_RECEIVED		0x00 /* RX level values (Interrupt trigger ) */
#define		_4_BYTE_RECEIVED		0x40
#define		_8_BYTE_RECEIVED		0x80
#define		_14_BYTE_RECEIVED		0xC0

/* RSLCR register   (UART line control register definition)                   */
#define		DIV_ENABLE				0x80
#define		TX_BREAK_ENABLE		0x40
#define		PARITY_ENABLE			0x08
#define		PARITY_MASK				0x30
#define		_1_STOP_BIT				0x00
#define		_2_STOP_BIT				0x04
#define		WORD_LENGTH_MASK		0x03
#define		ODD_PARITY				0x00	/* possible value for the parity */
#define		EVEN_PARITY				0x10
#define		PARITY_EQUAL1			0x20
#define		PARITY_EQUAL0			0x30
#define		_5_BITS_CHAR			0x00	/* possible value for the word length  */
#define		_6_BITS_CHAR			0x01
#define		_7_BITS_CHAR			0x02
#define		_8_BITS_CHAR			0x03

/* RSLSR Register   (UART line status register definition)                    */
#define		RX_FIFO_ERROR			0x80
#define		TXEMPTY					0x40
#define		HOLD_EMPTY				0x20
#define		BREAK						0x10
#define		FRAME_ERROR				0x08
#define		PARITY_ERROR			0x04
#define		OVERRUN_ERROR			0x02
#define		RX_READY					0x01

/* RSDLL Register   (UART clock divider low register definition)              */
/* note RSDLH is always 0x00 */
#define	RS_4800						0x18
#define	RS_9600						0x0C
#define	RS_19200					0x06
#define	RS_38400						0x03
#define	RS_57600						0x02
#define	RS_115200					0x01

/* RSCNT Register   (UART control register definition)                        */
#define		UART_PAD_ENABLE		0x02

/* PWMCNTL register                                                           */
#define PWMENB          0x80
#define MSK_PWMFREQ     0x03                /* mask on PWMFREQ field          */
#define PWM1_PADENB     0x40
#define PWM0_PADENB     0x20
#define MIRROR          0x10


/* LCDEECNTL1 register                                                        */
/* Bit ENABLE already defined                                                 */
#define LCDEE_ENABLE   0x80
#define DA1_DA0         0x40
#define MSK_LCDEEFREQ   0x03                /* mask on LCDEEFREQ field        */
#define LCDEE_PADENB    0x40

/* LCDEECNTL2 register                                                        */
#define SENDACK         0x01
#define RXACK           0x02
#define STOP            0x08
#define START           0x10
#define RX_LCDEE        0x20
#define TX_LCDEE        0x40

/* DIAGCNTL1 register                                                         */
#define DIAGL_PADENB    0x01
#define DIAGH_PADENB    0x02

/* DIAGCNTL2 register                                                         */
#define DLSEL           0x0F                /* mask on DLSEL field            */
#define DHSEL           0xF0                /* mask on DHSEL field            */