📄 registers.h
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/* * VEGA PLUS registers declaration * * Copyright (c) 2000 Canon Research France SA. * Emmanuel Raguet, mailto:raguet@crf.canon.fr * * The license and distribution terms for this file may be * found in found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * */#ifndef __LMREGS_H__#define __LMREGS_H__ /* * VARIABLE DECLARATION ****************************************************************************** *//* register area size */#define LM_REG_AREA_SIZ (0x4000/4) /*** Register mapping : defined by indexes in an array ***//*** NOTE : only 1 register every 4 byte address location (+ some holes) */#ifndef __asm__extern volatile unsigned long *Regs; /* Chip registers */#endif/****************************************************************************** * RADIO CONTROLLER BLOCK 0x0C00 - 0x0FFF * ****************************************************************************** */#define RC_BASE 0xC00#define RCCNTL ((RC_BASE+0x00)/4)#define RCIOCNTL0 ((RC_BASE+0x04)/4)#define RCIOCNTL1 ((RC_BASE+0x08)/4)#define SYNTCNTL0 ((RC_BASE+0x0C)/4)#define SYNTCNTL1 ((RC_BASE+0x10)/4)#define SYNTCNTL2 ((RC_BASE+0x14)/4)#define SYNTFCNTL ((RC_BASE+0x18)/4)#define SYNTPCNTL ((RC_BASE+0x1C)/4)#define RSSICNTL ((RC_BASE+0x20)/4)#define RSSIBASEL ((RC_BASE+0x24)/4)#define RSSIBASEH ((RC_BASE+0x28)/4)#define CURRSSI ((RC_BASE+0x2C)/4)#define RFSCAN ((RC_BASE+0x30)/4)#define CURRF ((RC_BASE+0x34)/4)#define CURRSSIA ((RC_BASE+0x38)/4)#define CURRSSIB ((RC_BASE+0x3C)/4)#define CURRSSIAB ((RC_BASE+0x40)/4)#define ADCDATAL ((RC_BASE+0x44)/4)#define ADCDATAH ((RC_BASE+0x48)/4)#define SLICECNTL ((RC_BASE+0x4C)/4)#define RCIOCNTL2 ((RC_BASE+0x50)/4)#define RCIOCNTL3 ((RC_BASE+0x54)/4)#define ADCREF1L ((RC_BASE+0x58)/4)#define ADCREF1H ((RC_BASE+0x5C)/4)#define ADCREF2L ((RC_BASE+0x60)/4)#define ADCREF2H ((RC_BASE+0x64)/4)#define ADCCNTL1 ((RC_BASE+0x68)/4)#define ADCCNTL2 ((RC_BASE+0x6C)/4)#define TESTREG ((RC_BASE+0x70)/4)#define SYNTLCNTL ((RC_BASE+0x74)/4)#define SYNTCNTL3 ((RC_BASE+0x78)/4)#define ADCPERIOD ((RC_BASE+0x7C)/4)#define SYNTIOCNTL ((RC_BASE+0x80)/4) /* added 30/08/99 *//* modified 30/08/99 by LHT */#define SHAPE0 ((RC_BASE+0x100)/4) /* previously 0x80 */#define SHAPE1 ((RC_BASE+0x104)/4)#define SHAPE2 ((RC_BASE+0x108)/4)#define SHAPE3 ((RC_BASE+0x10C)/4)#define SHAPE4 ((RC_BASE+0x110)/4)#define SHAPE5 ((RC_BASE+0x114)/4)#define SHAPE6 ((RC_BASE+0x118)/4)#define SHAPE7 ((RC_BASE+0x11C)/4)#define SHAPE8 ((RC_BASE+0x120)/4)#define SHAPE9 ((RC_BASE+0x124)/4)#define SHAPE10 ((RC_BASE+0x128)/4)#define SHAPE11 ((RC_BASE+0x12C)/4)#define SHAPE12 ((RC_BASE+0x130)/4)#define SHAPERMID ((RC_BASE+0x134)/4)#define SHAPERCNTL ((RC_BASE+0x138)/4)#define CURSHAPE ((RC_BASE+0x13C)/4)/** PLP BLOCK 0x1400 - 0x17FF */#define PLP_BASE 0x1400#define DCNTL0 ((PLP_BASE+0x00)/4)#define DCNTL1 ((PLP_BASE+0x04)/4)#define SYNC0 ((PLP_BASE+0x08)/4)#define SYNC1 ((PLP_BASE+0x0C)/4)#define RXSTARTDL ((PLP_BASE+0x10)/4)#define TXSTARTDL ((PLP_BASE+0x14)/4)#define RXSTOPDL ((PLP_BASE+0x1C)/4)#define RXSYNCT ((PLP_BASE+0x20)/4)#define HALF_TXSLOT ((PLP_BASE+0x24)/4)#define SCB_NUMBER ((PLP_BASE+0x28)/4)#define SCB_OPPNUMBER ((PLP_BASE+0x2C)/4)#define TXFRAME ((PLP_BASE+0x40)/4)#define MSLTPTR ((PLP_BASE+0x44)/4)#define CLOCK_CORR ((PLP_BASE+0x48)/4)#define PRESYNC ((PLP_BASE+0x4C)/4)#define PLPFINE ((PLP_BASE+0x50)/4)#define PLPINDEL ((PLP_BASE+0x54)/4)#define TXRXSKW ((PLP_BASE+0x58)/4)#define PLPALIN ((PLP_BASE+0x5C)/4)#define SUSPRFCNTL ((PLP_BASE+0x60)/4)#define SUSPCNTL ((PLP_BASE+0x64)/4)#define SUSPFC ((PLP_BASE+0x68)/4)#define TSTCNTL ((PLP_BASE+0x6C)/4)#define TSTDST ((PLP_BASE+0x70)/4)#define TSTTXD ((PLP_BASE+0x74)/4)#define TSTRXD ((PLP_BASE+0x78)/4)#define PLPID ((PLP_BASE+0x7C)/4)/** ENCRYPTION ENGINE 0x1800 - 0x1BFF */#define EE_BASE 0x1800#define EECNTL ((EE_BASE+0x00)/4)#define EEBASEL ((EE_BASE+0x08)/4)#define EEBASEH ((EE_BASE+0x0C)/4)#define MFL ((EE_BASE+0x10)/4)#define MFM ((EE_BASE+0x14)/4)#define MFH ((EE_BASE+0x18)/4)/** TELEPHONE ANSWERING DEVICE 0x1C00 - 0x1FFF */#define TAD_BASE 0x1C00#define TADCNTL ((TAD_BASE+0x00)/4)#define TADCODE1 ((TAD_BASE+0x04)/4)#define TADCODE2 ((TAD_BASE+0x08)/4)#define TADCODE3 ((TAD_BASE+0x0C)/4)#define TADSTAT ((TAD_BASE+0x10)/4)#define TADADDRL ((TAD_BASE+0x14)/4)#define TADADDRM ((TAD_BASE+0x18)/4)#define TADADDRH ((TAD_BASE+0x1C)/4)#define TADLEN ((TAD_BASE+0x20)/4)#define TADAUXDAT1 ((TAD_BASE+0x24)/4)#define TADAUXDAT2 ((TAD_BASE+0x28)/4)#define TADSHMEML ((TAD_BASE+0x2C)/4)#define TADSHMEMH ((TAD_BASE+0x30)/4)#define TADCMD ((TAD_BASE+0x34)/4)/** VOICE INTERFACE BLOCK 0x2000 - 0x23FF */#define PAINT_BASE 0x2000#define PAINTCNTL ((PAINT_BASE+0x00)/4)#define PAINTPLLCNTL ((PAINT_BASE+0x08)/4)#define PAINTPLLSTAT ((PAINT_BASE+0x0C)/4)#define VBAFECNTL ((PAINT_BASE+0x10)/4)#define VBAFEAMP ((PAINT_BASE+0x14)/4)#define VBAFEPREAMP ((PAINT_BASE+0x18)/4)#define PCMAUX ((PAINT_BASE+0x1C)/4)#define PCM0RX ((PAINT_BASE+0x20)/4)#define PCM0TX ((PAINT_BASE+0x24)/4)#define PCM1RX ((PAINT_BASE+0x28)/4)#define PCM1TX ((PAINT_BASE+0x2C)/4)#define ADPCM0RX ((PAINT_BASE+0x30)/4)#define ADPCM0TX ((PAINT_BASE+0x34)/4)#define ADPCM1RX ((PAINT_BASE+0x38)/4)#define ADPCM1TX ((PAINT_BASE+0x3C)/4)#define MPDCNTL ((PAINT_BASE+0x40)/4)#define MPDREADY ((PAINT_BASE+0x44)/4)#define MPDABS ((PAINT_BASE+0x48)/4)#define MPDS1 ((PAINT_BASE+0x4C)/4)#define MPDS2 ((PAINT_BASE+0x50)/4)#define HPPCMCNTL ((PAINT_BASE+0x60)/4)#define HPOUT ((PAINT_BASE+0x64)/4)#define HPIN ((PAINT_BASE+0x68)/4)#define PAINTBASE0 ((PAINT_BASE+0x70)/4)#define PAINTBASE1 ((PAINT_BASE+0x74)/4)#define G726AI0 ((PAINT_BASE+0x80)/4)#define G726AI1 ((PAINT_BASE+0x84)/4)#define G726GAIN0 ((PAINT_BASE+0x88)/4)#define G726GAIN1 ((PAINT_BASE+0x8C)/4)#define G726VOL ((PAINT_BASE+0x90)/4)#define G726GST ((PAINT_BASE+0x94)/4)#define G726CNTL0 ((PAINT_BASE+0x98)/4)#define G726CNTL1 ((PAINT_BASE+0x9C)/4)#define G726CHANNEL ((PAINT_BASE+0xA0)/4)#define G726CHANENB ((PAINT_BASE+0xA4)/4)/** GENERAL REGISTERS BLOCK 0x2800 - 0x2CFF */#define MISC_BASE 0x2800#define CHIPID ((MISC_BASE+0x00)/4)#define DEVICEID ((MISC_BASE+0x04)/4)#define IOACNTL ((MISC_BASE+0x10)/4)#define IOADATA ((MISC_BASE+0x18)/4)#define IOBCNTL ((MISC_BASE+0x20)/4)#define IOBDATA ((MISC_BASE+0x28)/4)#define IOCCNTL1 ((MISC_BASE+0x30)/4)#define IOCCNTL2 ((MISC_BASE+0x34)/4)#define IOCDATA ((MISC_BASE+0x38)/4)#define IODCNTL1 ((MISC_BASE+0x40)/4)#define IODCNTL2 ((MISC_BASE+0x44)/4)#define IODDATA ((MISC_BASE+0x48)/4)#define IOECNTL1 ((MISC_BASE+0x50)/4)#define IOECNTL2 ((MISC_BASE+0x54)/4)#define IOEDATA ((MISC_BASE+0x58)/4)#define IOFCNTL ((MISC_BASE+0x60)/4)#define IOFDATA ((MISC_BASE+0x68)/4)#define IOGCNTL ((MISC_BASE+0x70)/4)#define IOGDATA ((MISC_BASE+0x78)/4)#define IOHCNTL ((MISC_BASE+0x80)/4)#define IOHDATA ((MISC_BASE+0x88)/4)#define RINGCNTL ((MISC_BASE+0x90)/4)#define RINGFREQ ((MISC_BASE+0x94)/4)#define RSCNTL ((MISC_BASE+0xA0)/4)/*#ifndef PRODUCT_VERSION*/ #define RSRXD ((MISC_BASE+0xA4)/4)#define RSTXD ((MISC_BASE+0xA8)/4)/*#endif*/#define PWMCNTL ((MISC_BASE+0xB0)/4)#define PWMTIMER0 ((MISC_BASE+0xB4)/4)#define PWMTIMER1 ((MISC_BASE+0xB8)/4)#define LCDEECNTL1 ((MISC_BASE+0xC0)/4)#define LCDEECNTL2 ((MISC_BASE+0xC4)/4)#define LCDEEDAIN ((MISC_BASE+0xC8)/4)#define LCDEEDAOUT ((MISC_BASE+0xCC)/4)#define KEYROW ((MISC_BASE+0xE0)/4)#define KEYCOL ((MISC_BASE+0xE4)/4)#define KEYDEBOUNCE ((MISC_BASE+0xE8)/4)#define DIAGCNTL1 ((MISC_BASE+0xEC)/4)#define DIAGCNTL2 ((MISC_BASE+0xF0)/4)#define CLKCNTL ((MISC_BASE+0xF4)/4)#define OSCCOR ((MISC_BASE+0xF8)/4)/* PRODUCT_VERSION */ /* Added 30/08/99 : New Control register for UART control */#define UART_BASE 0x3000#define RSRBR ((UART_BASE+0x00)/4)#define RSTHR ((UART_BASE+0x00)/4)#define RSIER ((UART_BASE+0x04)/4)#define RSIIR ((UART_BASE+0x08)/4)#define RSFCR ((UART_BASE+0x08)/4)#define RSLCR ((UART_BASE+0x0C)/4)#define RSLSR ((UART_BASE+0x14)/4)#define RSDLL ((UART_BASE+0x00)/4)#define RSDLH ((UART_BASE+0x04)/4)#define RSCNT ((UART_BASE+0x20)/4)/*PRODUCT_VERSION*/ /** THUMB and INTERFACES BLOCK 0x3400 - 0x4FFF */#define TIM_BASE 0x3400#define WDCNTL ((TIM_BASE+0x00)/4)#define TIMERLOAD0 ((TIM_BASE+0x80)/4)#define TIMER0 ((TIM_BASE+0x8C)/4)#define TIMERCNTL0 ((TIM_BASE+0x98)/4)#define TIMERLOAD1 ((TIM_BASE+0xA0)/4)#define TIMER1 ((TIM_BASE+0xAC)/4)#define TIMERCNTL1 ((TIM_BASE+0xB8)/4)#define INTC_BASE 0x3800#define INTMASK ((INTC_BASE+0x20)/4)#define INTSTAT ((INTC_BASE+0x24)/4)#define INTACK ((INTC_BASE+0x24)/4)#define INTACK2 ((INTC_BASE+0x24))#define INTIS ((INTC_BASE+0x28)/4)#define INTIS2 ((INTC_BASE+0x28))#define INTHPAI ((INTC_BASE+0x00)/4)#define INTHPAI2 ((INTC_BASE+0x00))#define INTLEVEL ((INTC_BASE+0x04)/4)#define INTEOI ((INTC_BASE+0x08)/4)#define INTEOI2 ((INTC_BASE+0x08))#define INTMASKALL ((INTC_BASE+0x0C)/4)#define INTTAB ((INTC_BASE+0x10)/4)#define INTCNTL0 ((INTC_BASE+0x80)/4)#define INTCNTL1 ((INTC_BASE+0x84)/4)#define INTCNTL2 ((INTC_BASE+0x88)/4)#define INTCNTL3 ((INTC_BASE+0x8C)/4)#define INTCNTL4 ((INTC_BASE+0x90)/4)#define INTCNTL5 ((INTC_BASE+0x94)/4)#define INTCNTL6 ((INTC_BASE+0x98)/4)#define INTCNTL7 ((INTC_BASE+0x9C)/4)#define INTCNTL8 ((INTC_BASE+0xA0)/4)#define INTCNTL9 ((INTC_BASE+0xA4)/4)#define INTCNTL10 ((INTC_BASE+0xA8)/4)#define INTCNTL11 ((INTC_BASE+0xAC)/4)#define INTCNTL12 ((INTC_BASE+0xB0)/4)#define INTCNTL13 ((INTC_BASE+0xB4)/4)#define INTCNTL14 ((INTC_BASE+0xB8)/4)#define INTCNTL15 ((INTC_BASE+0xBC)/4)#define INTGCNTL ((INTC_BASE+0x7C)/4)/* these "define" are used for the asm code of int managment */#define INTPHAI3 0xF3800#define INTSTAT3 0xF3824#define INTIS3 0xF3828#define INTACK3 0xF3824#define INTEOI3 0xF3808#define TI_BASE 0x3C00#define CSCNTL0_0 ((TI_BASE+0x00)/4)#define CSCNTL0_1 ((TI_BASE+0x04)/4)#define CSCNTL0_2 ((TI_BASE+0x08)/4)#define CSCNTL0_3 ((TI_BASE+0x0C)/4)#define CSCNTL0_4 ((TI_BASE+0x10)/4)#define CSCNTL0_5 ((TI_BASE+0x14)/4)#define CSCNTL0_6 ((TI_BASE+0x18)/4)#define CSCNTL1_0 ((TI_BASE+0x20)/4)#define CSCNTL1_1 ((TI_BASE+0x24)/4)#define CSCNTL1_2 ((TI_BASE+0x28)/4)#define CSCNTL1_3 ((TI_BASE+0x2C)/4)#define CSCNTL1_4 ((TI_BASE+0x30)/4)#define CSCNTL1_5 ((TI_BASE+0x34)/4)#define CSCNTL1_6 ((TI_BASE+0x38)/4)#define CSGCNTL ((TI_BASE+0x40)/4)#define MUXADCNTL ((TI_BASE+0x48)/4)#define PORTCNTL ((TI_BASE+0x60)/4)#define DCC ((TI_BASE+0x78)/4)#define BRK0 ((TI_BASE+0x100)/4)#define BRK1 ((TI_BASE+0x104)/4)#define BRK2 ((TI_BASE+0x108)/4)#define BRK3 ((TI_BASE+0x10C)/4)#define BRK4 ((TI_BASE+0x110)/4)#define BRK5 ((TI_BASE+0x114)/4)#define BRK6 ((TI_BASE+0x118)/4)#define BRK7 ((TI_BASE+0x11C)/4)#define BRKMSK ((TI_BASE+0x140)/4)#define BRKSTAT ((TI_BASE+0x144)/4)#define SLEEPTIMER ((TI_BASE+0x204)/4)#define SLEEPCNTL ((TI_BASE+0x208)/4)/****************************************************************************** * BIT MASKS for Chip registers ****************************************************************************** *//** TELEPHONE ANSWERING DEVICE BLOCK (TAD) *//* TADCNTL register */#define IRQCNTL 0x01#define CE_CNTL 0x02#define MSKTAD 0x04#define TAD_PAD_ENB 0x40#define TADENB 0x80/* TADSTAT register */#define RBN 0x01#define TRANSFER 0x02#define ACTIVE 0x04/* TADCMD register */#define MSK_TADCMD 0x0F /* Mask on TADCMD */#define CONTINUE 0x10/** RADIO CONTROLER BLOCK (RC3) *//* SLICECNTL register */#define MSK_SLICEDL 0x07 /* Mask on SLICEDL field */#define MSK_SCNTL 0x18 /* Mask on SCNTL field */#define SELOCK 0x20#define MSK_MUXSLICE 0xC0/* RCIOCNTL0 register */#define D2SBYPASS 0x01#define DRBYPASS 0x02#define RXINV 0x04#define SELANT 0x10#define ANT 0x20#define LDINV0 0x40#define LDINV1 0x80⌨️ 快捷键说明
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