cpu.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

typedef struct {
    double      some_float_register[2];
} Context_Control_fp;

typedef struct {
    unsigned32 special_interrupt_register;
} CPU_Interrupt_frame;


/*
 *  The following table contains the information required to configure
 *  the XXX processor specific parameters.
 *
 *  NOTE: The interrupt_stack_size field is required if
 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
 *
 *        The pretasking_hook, predriver_hook, and postdriver_hook,
 *        and the do_zero_of_workspace fields are required on ALL CPUs.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

typedef struct {
  void       (*pretasking_hook)( void );
  void       (*predriver_hook)( void );
  void       (*postdriver_hook)( void );
  void       (*idle_task)( void );
  boolean      do_zero_of_workspace;
  unsigned32   idle_task_stack_size;
  unsigned32   interrupt_stack_size;
  unsigned32   extra_mpci_receive_server_stack;
  void *     (*stack_allocate_hook)( unsigned32 );
  void       (*stack_free_hook)( void* );
}   rtems_cpu_table;

/*
 *  This variable is optional.  It is used on CPUs on which it is difficult
 *  to generate an "uninitialized" FP context.  It is filled in by
 *  _CPU_Initialize and copied into the task's FP context area during
 *  _CPU_Context_Initialize.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;

/*
 *  On some CPUs, RTEMS supports a software managed interrupt stack.
 *  This stack is allocated by the Interrupt Manager and the switch
 *  is performed in _ISR_Handler.  These variables contain pointers
 *  to the lowest and highest addresses in the chunk of memory allocated
 *  for the interrupt stack.  Since it is unknown whether the stack
 *  grows up or down (in general), this give the CPU dependent
 *  code the option of picking the version it wants to use.
 *
 *  NOTE: These two variables are required if the macro
 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
SCORE_EXTERN void               *_CPU_Interrupt_stack_high;

/*
 *  With some compilation systems, it is difficult if not impossible to
 *  call a high-level language routine from assembly language.  This
 *  is especially true of commercial Ada compilers and name mangling
 *  C++ ones.  This variable can be optionally defined by the CPU porter
 *  and contains the address of the routine _Thread_Dispatch.  This
 *  can make it easier to invoke that routine at the end of the interrupt
 *  sequence (if a dispatch is necessary).
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();

/*
 *  Nothing prevents the porter from declaring more CPU specific variables.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

/* XXX: if needed, put more variables here */

/*
 *  The size of the floating point context area.  On some CPUs this
 *  will not be a "sizeof" because the format of the floating point
 *  area is not defined -- only the size is.  This is usually on
 *  CPUs with a "floating point save context" instruction.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )

/*
 *  Amount of extra stack (above minimum stack size) required by
 *  system initialization thread.  Remember that in a multiprocessor
 *  system the system intialization thread becomes the MP server thread.
 *
 *  H8300 Specific Information:
 *
 *  It is highly unlikely the H8300 will get used in a multiprocessor system.
 */

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 

/*
 *  This defines the number of entries in the ISR_Vector_table managed
 *  by RTEMS.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)

/*
 *  This is defined if the port has a special way to report the ISR nesting
 *  level.  Most ports maintain the variable _ISR_Nest_level.
 */

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

/*
 *  Should be large enough to run all RTEMS tests.  This insures
 *  that a "reasonable" small application should not have any problems.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define CPU_STACK_MINIMUM_SIZE          (1536)

/*
 *  CPU's worst alignment requirement for data types on a byte boundary.  This
 *  alignment does not take into account the requirements for the stack.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define CPU_ALIGNMENT              8

/*
 *  This number corresponds to the byte alignment requirement for the
 *  heap handler.  This alignment requirement may be stricter than that
 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
 *  common for the heap to follow the same alignment requirement as
 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
 *  then this should be set to CPU_ALIGNMENT.
 *
 *  NOTE:  This does not have to be a power of 2.  It does have to
 *         be greater or equal to than CPU_ALIGNMENT.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT

/*
 *  This number corresponds to the byte alignment requirement for memory
 *  buffers allocated by the partition manager.  This alignment requirement
 *  may be stricter than that for the data types alignment specified by
 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
 *
 *  NOTE:  This does not have to be a power of 2.  It does have to
 *         be greater or equal to than CPU_ALIGNMENT.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT

/*
 *  This number corresponds to the byte alignment requirement for the
 *  stack.  This alignment requirement may be stricter than that for the
 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
 *  is strict enough for the stack, then this should be set to 0.
 *
 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define CPU_STACK_ALIGNMENT        2

/*
 *  ISR handler macros
 */

/*
 *  Support routine to initialize the RTEMS vector table after it is allocated.
 */

#define _CPU_Initialize_vectors()

/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
   Note requires ISR_Level be unsigned16 or assembler croaks.
*/

#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )


/*
 *  Disable all interrupts for an RTEMS critical section.  The previous
 *  level is returned in _level.
 */

#define _CPU_ISR_Disable( _isr_cookie ) \
  do { \
    asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  : "r" (_isr_cookie) ); \
  } while (0)


/*
 *  Enable interrupts to the previois level (returned by _CPU_ISR_Disable).
 *  This indicates the end of an RTEMS critical section.  The parameter
 *  _level is not modified.
 */


#define _CPU_ISR_Enable( _isr_cookie )  \
  do { \
    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
  } while (0)


/*
 *  This temporarily restores the interrupt to _level before immediately
 *  disabling them again.  This is used to divide long RTEMS critical
 *  sections into two or more parts.  The parameter _level is not
 * modified.
 */


#define _CPU_ISR_Flash( _isr_cookie ) \
  do { \
    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
  } while (0)

/* end of ISR handler macros */

#else /* modern gcc version */

/*
 *  Disable all interrupts for an RTEMS critical section.  The previous
 *  level is returned in _level.
 *
 *  H8300 Specific Information:
 *
 *  XXX  
 */

#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Disable( _isr_cookie ) \
  do { \
    unsigned char __ccr; \
    asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \
             : "=m" (__ccr) : "0" (__ccr) ); \
    (_isr_cookie) = __ccr; \
  } while (0) 
#else
#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
#endif


/*
 *  Enable interrupts to the previois level (returned by _CPU_ISR_Disable).
 *  This indicates the end of an RTEMS critical section.  The parameter
 *  _level is not modified.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Enable( _isr_cookie )  \
  do { \
    unsigned char __ccr = (unsigned char) (_isr_cookie); \
    asm volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
  } while (0) 
#else
#define _CPU_ISR_Enable( _isr_cookie )
#endif

/*
 *  This temporarily restores the interrupt to _level before immediately
 *  disabling them again.  This is used to divide long RTEMS critical
 *  sections into two or more parts.  The parameter _level is not
 *  modified.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Flash( _isr_cookie ) \
  do { \
    unsigned char __ccr = (unsigned char) (_isr_cookie); \
    asm volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
  } while (0) 
#else
#define _CPU_ISR_Flash( _isr_cookie )
#endif

#endif /* end of old gcc */


/*
 *  Map interrupt level in task mode onto the hardware that the CPU
 *  actually provides.  Currently, interrupt levels which do not
 *  map onto the CPU in a generic fashion are undefined.  Someday,
 *  it would be nice if these were "mapped" by the application
 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
 *  8 - 255 would be available for bsp/application specific meaning.
 *  This could be used to manage a programmable interrupt controller
 *  via the rtems_task_mode directive.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */

#define _CPU_ISR_Set_level( _new_level ) \
  { \
    if ( _new_level ) asm volatile ( "orc #0x80,ccr\n" ); \
    else              asm volatile ( "andc #0x7f,ccr\n" ); \
  }

unsigned32 _CPU_ISR_Get_level( void );

/* end of ISR handler macros */

/* Context handler macros */

/*
 *  Initialize the context to a state suitable for starting a
 *  task after a context restore operation.  Generally, this
 *  involves:
 *
 *     - setting a starting address
 *     - preparing the stack
 *     - preparing the stack and frame pointers
 *     - setting the proper interrupt level in the context
 *     - initializing the floating point context
 *
 *  This routine generally does not set any unnecessary register
 *  in the context.  The state of the "general data" registers is
 *  undefined at task start time.
 *
 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
 *        point thread.  This is typically only used on CPUs where the
 *        FPU may be easily disabled by software such as on the SPARC
 *        where the PSR contains an enable FPU bit.
 *
 *  H8300 Specific Information:
 *
 *  XXX
 */


#define CPU_CCR_INTERRUPTS_ON  0x80
#define CPU_CCR_INTERRUPTS_OFF 0x00

#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
                                   _isr, _entry_point, _is_fp ) \
  /* Locate Me */ \
  do { \
    unsigned32 _stack; \
    \