m68302.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

    rtems_unsigned16	character[8];	/* Control Characters 1 through 8*/
} m302_SCC_UartSpecific_t;
/*
 *  This definition allows for the checking of receive buffers
 *  for errors.
 */

#define RCV_ERR    0x003F

/*
 * UART receive buffer descriptor bit definitions.
 * Section 4.5.11.14
 */
#define RBIT_UART_CTRL   (1<<11)	/* buffer contains a control char */
#define RBIT_UART_ADDR   (1<<10)	/* first byte contains an address */
#define RBIT_UART_MATCH  (1<<9)		/* indicates which addr char matched */
#define RBIT_UART_IDLE   (1<<8)		/* buffer closed due to IDLE sequence */
#define RBIT_UART_BR     (1<<5)		/* break sequence was received */
#define RBIT_UART_FR     (1<<4)		/* framing error was received */
#define RBIT_UART_PR     (1<<3)		/* parity error was received */
#define RBIT_UART_OV     (1<<1)		/* receiver overrun occurred */
#define RBIT_UART_CD     (1<<0)		/* carrier detect lost */
#define RBIT_UART_STATUS 0x003B		/* all status bits */

/*
 * UART transmit buffer descriptor bit definitions.
 * Section 4.5.11.15
 */
#define RBIT_UART_CR       (1<<11)	/* clear-to-send report
					 * this results in two idle bits
					 * between back-to-back frames
					 */
#define RBIT_UART_A        (1<<10)	/* buffer contains address characters
					 * only valid in multidrop mode (UM0=1)
					 */
#define RBIT_UART_PREAMBLE (1<<9)	/* send preamble before data */
#define RBIT_UART_CTS_LOST (1<<0)	/* CTS lost */

/*
 * UART event register
 * Section 4.5.11.16
 */
#define M302_UART_EV_CTS   (1<<7)	/* CTS status changed */
#define M302_UART_EV_CD    (1<<6)	/* carrier detect status changed */
#define M302_UART_EV_IDL   (1<<5)	/* IDLE sequence status changed */
#define M302_UART_EV_BRK   (1<<4)	/* break character was received */
#define M302_UART_EV_CCR   (1<<3)	/* control character received */
#define M302_UART_EV_TX    (1<<1)	/* buffer has been transmitted */
#define M302_UART_EV_RX    (1<<0)	/* buffer has been received */


/*
 * HDLC-Specific SCC Parameter RAM
 * Section 4.5.12.3
 *
 * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC
 * c_mask_h is a don't care  for 16-bit CRC, 0x20E2 for 32-bit CRC
 */
typedef struct {
    rtems_unsigned16	rcrc_l;		/* Temp Receive CRC Low */
    rtems_unsigned16	rcrc_h;		/* Temp Receive CRC High */
    rtems_unsigned16	c_mask_l;	/* CRC Mask Low */
    rtems_unsigned16	c_mask_h;	/* CRC Mask High */
    rtems_unsigned16	tcrc_l;		/* Temp Transmit CRC Low */
    rtems_unsigned16	tcrc_h;		/* Temp Transmit CRC High */

    rtems_unsigned16	disfc;		/* Discard Frame Counter */
    rtems_unsigned16	crcec;		/* CRC Error Counter */
    rtems_unsigned16	abtsc;		/* Abort Sequence Counter */
    rtems_unsigned16	nmarc;		/* Nonmatching Address Received Cntr */
    rtems_unsigned16	retrc;		/* Frame Retransmission Counter */

    rtems_unsigned16	mflr;		/* Maximum Frame Length Register */
    rtems_unsigned16	max_cnt;	/* Maximum_Length Counter */

    rtems_unsigned16	hmask;		/* User Defined Frame Address Mask */
    rtems_unsigned16	haddr1;		/* User Defined Frame Address */
    rtems_unsigned16	haddr2;		/* " */
    rtems_unsigned16	haddr3;		/* " */
    rtems_unsigned16	haddr4;		/* " */
} m302_SCC_HdlcSpecific_t;
/*
 * HDLC receiver buffer descriptor bit definitions
 * Section 4.5.12.10
 */
#define RBIT_HDLC_EMPTY_BIT  0x8000	/* buffer associated with BD is empty */
#define RBIT_HDLC_LAST_BIT   0x0800	/* buffer is last in a frame */
#define RBIT_HDLC_FIRST_BIT  0x0400	/* buffer is first in a frame */
#define RBIT_HDLC_FRAME_LEN  0x0020	/* receiver frame length violation */
#define RBIT_HDLC_NONOCT_Rx  0x0010	/* received non-octet aligned frame */
#define RBIT_HDLC_ABORT_SEQ  0x0008	/* received abort sequence */
#define RBIT_HDLC_CRC_ERROR  0x0004	/* frame contains a CRC error */
#define RBIT_HDLC_OVERRUN    0x0002	/* receiver overrun occurred */
#define RBIT_HDLC_CD_LOST    0x0001	/* carrier detect lost */

/*
 * HDLC transmit buffer descriptor bit definitions
 * Section 4.5.12.11
 */
#define RBIT_HDLC_READY_BIT  0x8000	/* buffer is ready to transmit */
#define RBIT_HDLC_EXT_BUFFER 0x4000	/* buffer is in external memory */
#define RBIT_HDLC_WRAP_BIT   0x2000	/* last buffer in bd table, so wrap */
#define RBIT_HDLC_WAKE_UP    0x1000	/* interrupt when buffer serviced */
#define RBIT_HDLC_LAST_BIT   0x0800	/* buffer is last in the frame */
#define RBIT_HDLC_TxCRC_BIT  0x0400	/* transmit a CRC sequence */
#define RBIT_HDLC_UNDERRUN   0x0002	/* transmitter underrun */
#define RBIT_HDLC_CTS_LOST   0x0001	/* CTS lost */

/*
 * HDLC event register bit definitions
 * Section 4.5.12.12
 */
#define RBIT_HDLC_CTS   0x80		/* CTS status changed */
#define RBIT_HDLC_CD    0x40		/* carrier detect status changed */
#define RBIT_HDLC_IDL   0x20		/* IDLE sequence status changed */
#define RBIT_HDLC_TXE   0x10		/* transmit error */
#define RBIT_HDLC_RXF   0x08		/* received frame */
#define RBIT_HDLC_BSY  0x04		/* frame rcvd and discarded due to
					 * lack of buffers
					 */
#define RBIT_HDLC_TXB    0x02		/* buffer has been transmitted */
#define RBIT_HDLC_RXB    0x01		/* received buffer */



typedef struct {
    m302_SCC_bd_table_t          bd;	/* +000 Buffer Descriptor Table */
    m302_SCC_parameters_t        parm;	/* +080 Common Parameter RAM */
    union {				/* +09C Protocol-Specific Parm RAM */
	m302_SCC_UartSpecific_t  uart;
	m302_SCC_HdlcSpecific_t  hdlc;
    } prot;
    rtems_unsigned8	   res[0x040];	/* +0C0 reserved, (not implemented) */
} m302_SCC_t;


/*
 * Common SCC Registers
 */
typedef struct {
    rtems_unsigned16	res1;
    rtems_unsigned16	scon;	/* SCC Configuration Register        4.5.2 */
    rtems_unsigned16	scm;	/* SCC Mode Register                 4.5.3 */
    rtems_unsigned16	dsr;	/* SCC Data Synchronization Register 4.5.4 */
    rtems_unsigned8	scce;	/* SCC Event Register  4.5.8.1 */
    rtems_unsigned8	res2;
    rtems_unsigned8	sccm;	/* SCC Mask Register   4.5.8.2 */
    rtems_unsigned8	res3;
    rtems_unsigned8	sccs;	/* SCC Status Register 4.5.8.3 */
    rtems_unsigned8	res4;
    rtems_unsigned16	res5;
} m302_SCC_Registers_t;

/*
 * SCON - SCC Configuration Register
 * Section 4.5.2
 */
#define RBIT_SCON_WOMS	(1<<15)		/* Wired-OR Mode Select (NMSI mode only)
					 * When set, the TXD driver is an
					 * open-drain output */
#define RBIT_SCON_EXTC	(1<<14)		/* External Clock Source */
#define RBIT_SCON_TCS	(1<<13)		/* Transmit Clock Source */
#define RBIT_SCON_RCS	(1<<12)		/* Receive Clock Source */

/*
 * SCM - SCC Mode Register bit definitions
 * Section 4.5.3
 * The parameter-specific mode bits occupy bits 15 through 6.
 */
#define RBIT_SCM_ENR	(1<<3)		/* Enable receiver */
#define RBIT_SCM_ENT	(1<<2)		/* Enable transmitter */


/*
 * Internal MC68302 Registers
 * starts at offset 0x800 from dual-port RAM base
 * Section 2.8
 */
typedef struct {
    /* offset +800 */
    rtems_unsigned16	res0;
    rtems_unsigned16	cmr;		/* IDMA Channel Mode Register */
    rtems_unsigned32	sapr;		/* IDMA Source Address Pointer */
    rtems_unsigned32	dapr;		/* IDMA Destination Address Pointer */
    rtems_unsigned16	bcr;		/* IDMA Byte Count Register */
    rtems_unsigned8	csr;		/* IDMA Channel Status Register */
    rtems_unsigned8	res1;
    rtems_unsigned8	fcr;		/* IDMA Function Code Register */
    rtems_unsigned8	res2;

    /* offset +812 */
    rtems_unsigned16	gimr;		/* Global Interrupt Mode Register */
    rtems_unsigned16	ipr;		/* Interrupt Pending Register */
    rtems_unsigned16	imr;		/* Interrupt Mask Register */
    rtems_unsigned16	isr;		/* Interrupt In-Service Register */
    rtems_unsigned16	res3;
    rtems_unsigned16	res4;

    /* offset +81e */
    rtems_unsigned16	pacnt;		/* Port A Control Register */
    rtems_unsigned16	paddr;		/* Port A Data Direction Register */
    rtems_unsigned16	padat;		/* Port A Data Register */
    rtems_unsigned16	pbcnt;		/* Port B Control Register */
    rtems_unsigned16	pbddr;		/* Port B Data Direction Register */
    rtems_unsigned16	pbdat;		/* Port B Data Register */
    rtems_unsigned16	res5;

    /* offset +82c */
    rtems_unsigned16	res6;
    rtems_unsigned16	res7;

    rtems_unsigned16	br0;		/* Base Register   (CS0) */
    rtems_unsigned16	or0;		/* Option Register (CS0) */
    rtems_unsigned16	br1;		/* Base Register   (CS1) */
    rtems_unsigned16	or1;		/* Option Register (CS1) */
    rtems_unsigned16	br2;		/* Base Register   (CS2) */
    rtems_unsigned16	or2;		/* Option Register (CS2) */
    rtems_unsigned16	br3;		/* Base Register   (CS3) */
    rtems_unsigned16	or3;		/* Option Register (CS3) */

    /* offset +840 */
    rtems_unsigned16	tmr1;		/* Timer Unit 1 Mode Register */
    rtems_unsigned16	trr1;		/* Timer Unit 1 Reference Register */
    rtems_unsigned16	tcr1;		/* Timer Unit 1 Capture Register */
    rtems_unsigned16	tcn1;		/* Timer Unit 1 Counter */
    rtems_unsigned8	res8;
    rtems_unsigned8	ter1;		/* Timer Unit 1 Event Register */
    rtems_unsigned16	wrr;		/* Watchdog Reference Register */
    rtems_unsigned16	wcn;		/* Watchdog Counter */
    rtems_unsigned16	res9;
    rtems_unsigned16	tmr2;		/* Timer Unit 2 Mode Register */
    rtems_unsigned16	trr2;		/* Timer Unit 2 Reference Register */
    rtems_unsigned16	tcr2;		/* Timer Unit 2 Capture Register */
    rtems_unsigned16	tcn2;		/* Timer Unit 2 Counter */
    rtems_unsigned8	resa;
    rtems_unsigned8	ter2;		/* Timer Unit 2 Event Register */
    rtems_unsigned16	resb;
    rtems_unsigned16	resc;
    rtems_unsigned16	resd;

    /* offset +860 */
    rtems_unsigned8	cr;		/* Command Register */
    rtems_unsigned8	rese[0x1f];

    /* offset +880, +890, +8a0 */
    m302_SCC_Registers_t scc[3];	/* SCC1, SCC2, SCC3 Registers */

    /* offset +8b0 */
    rtems_unsigned16	spmode;		/* SCP,SMC Mode and Clock Cntrl Reg */
    rtems_unsigned16	simask;		/* Serial Interface Mask Register */
    rtems_unsigned16	simode;		/* Serial Interface Mode Register */
} m302_internalReg_t ;


/*
 * MC68302 dual-port RAM structure.
 * (Includes System RAM, Parameter RAM, and Internal Registers).
 * Section 2.8
 */
typedef struct {
    rtems_unsigned8	mem[0x240];	/* +000 User Data Memory */
    rtems_unsigned8	res1[0x1c0];	/* +240 reserved, (not implemented) */
    m302_SCC_t		scc1;		/* +400 SCC1 */
    m302_SCC_t		scc2;		/* +500 SCC2 */
    m302_SCC_t		scc3;		/* +600 SCC3 */
    rtems_unsigned8	res2[0x100];	/* +700 reserved, (not implemented) */
    m302_internalReg_t	reg;		/* [phone] Internal Registers */
} m302_dualPortRAM_t;

/* some useful defines the some of the registers above */
  

/* ----
   MC68302 Chip Select Registers
      p3-46 2nd Edition

 */
#define BR_ENABLED     1
#define BR_DISABLED    0
#define BR_FC_NULL     0
#define BR_READ_ONLY   0
#define BR_READ_WRITE  2
#define OR_DTACK_0     0x0000
#define OR_DTACK_1     0x2000
#define OR_DTACK_2     0x4000
#define OR_DTACK_3     0x6000
#define OR_DTACK_4     0x8000
#define OR_DTACK_5     0xA000
#define OR_DTACK_6     0xC000
#define OR_DTACK_EXT   0xE000
#define OR_SIZE_64K    0x1FE0
#define OR_SIZE_128K   0x1FC0
#define OR_SIZE_256K   0x1F80
#define OR_SIZE_512K   0x1F00
#define OR_SIZE_1M     0x1E00
#define OR_SIZE_2M     0x1C00
#define OR_MASK_RW     0x0000
#define OR_NO_MASK_RW  0x0002
#define OR_MASK_FC     0x0000
#define OR_NO_MASK_FC  0x0001

#define MAKE_BR(base_address, enable, rw, fc) \
    ((base_address >> 11) | fc | rw | enable)

#define MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) \
    (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask)

#define __REG_CAT(r, n) r ## n
#define WRITE_BR(csel, base_address, enable, rw, fc) \
          __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc)
#define WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) \
          __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask)

/* ----
   MC68302 Watchdog Timer Enable Bit

 */
#define WATCHDOG_ENABLE    (1)
#define WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0)
#define WATCHDOG_TOGGLE()  (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD)
#define DISABLE_WATCHDOG() (m302.reg.wrr = 0)

/*
 * Declare the variable that's used to reference the variables in
 * the dual-port RAM.
 */
extern volatile m302_dualPortRAM_t m302;

#endif
/* end of include file */