m68302.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*
 *------------------------------------------------------------------
 *
 *	m68302.h - Definitions for Motorola MC68302 processor.
 *
 * Section references in this file refer to revision 2 of Motorola's
 * "MC68302 Integrated Multiprotocol Processor User's Manual".
 * (Motorola document MC68302UM/AD REV 2.)
 *
 * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k
 * on 17 February, 1993.
 *
 * Copyright 1995 David W. Glessner.
 *
 * Redistribution and use in source and binary forms are permitted
 * provided that the following conditions are met:
 * 1. Redistribution of source code and documentation must retain
 *    the above copyright notice, this list of conditions and the
 *    following disclaimer.
 * 2. The name of the author may not be used to endorse or promote
 *    products derived from this software without specific prior
 *    written permission.
 *
 * This software is provided "AS IS" without warranty of any kind,
 * either expressed or implied, including, but not limited to, the
 * implied warranties of merchantability, title and fitness for a
 * particular purpose.
 *
 *
 *  $Id: m68302.h,v 1.6 2000/10/19 15:32:20 joel Exp $
 *
 *------------------------------------------------------------------
 */

#ifndef __MOTOROLA_MC68302_DEFINITIONS_h
#define __MOTOROLA_MC68302_DEFINITIONS_h

/*
 * BAR - Base Address Register
 * Section 2.7
 */
#define M302_BAR	(*((volatile rtems_unsigned16 *) 0xf2))

/*
 * SCR - System Control Register
 * Section 3.8.1
 */
#define M302_SCR	(*((volatile rtems_unsigned32 *) 0xf4))
/*
 * SCR bits
 */
#define RBIT_SCR_IPA		0x08000000
#define RBIT_SCR_HWT		0x04000000
#define RBIT_SCR_WPV		0x02000000
#define RBIT_SCR_ADC		0x01000000

#define RBIT_SCR_ERRE		0x00400000
#define RBIT_SCR_VGE		0x00200000
#define RBIT_SCR_WPVE		0x00100000
#define RBIT_SCR_RMCST		0x00080000
#define RBIT_SCR_EMWS		0x00040000
#define RBIT_SCR_ADCE		0x00020000
#define RBIT_SCR_BCLM		0x00010000

#define RBIT_SCR_FRZW		0x00008000
#define RBIT_SCR_FRZ2		0x00004000
#define RBIT_SCR_FRZ1		0x00002000
#define RBIT_SCR_SAM		0x00001000
#define RBIT_SCR_HWDEN		0x00000800
#define RBIT_SCR_HWDCN2		0x00000400
#define RBIT_SCR_HWDCN1		0x00000200  /* 512 clocks */
#define RBIT_SCR_HWDCN0		0x00000100  /* 128 clocks */

#define RBIT_SCR_LPREC		0x00000080
#define RBIT_SCR_LPP16		0x00000040
#define RBIT_SCR_LPEN		0x00000020
#define RBIT_SCR_LPCLKDIV	0x0000001f


/*
 * 68000 interrupt and trap vector numbers
 */
#define M68K_IVEC_BUS_ERROR		 2
#define M68K_IVEC_ADDRESS_ERROR		 3
#define M68K_IVEC_ILLEGAL_OPCODE	 4
#define M68K_IVEC_ZERO_DIVIDE		 5
#define M68K_IVEC_CHK			 6
#define M68K_IVEC_TRAPV			 7
#define M68K_IVEC_PRIVILEGE		 8
#define M68K_IVEC_TRACE			 9
#define M68K_IVEC_LINE_A		10
#define M68K_IVEC_LINE_F		11
/*	Unassigned, Reserved		12-14 */
#define M68K_IVEC_UNINITIALIZED_INT	15
/*	Unassigned, Reserved		16-23 */
#define M68K_IVEC_SPURIOUS_INT		24

#define M68K_IVEC_LEVEL1_AUTOVECTOR	25
#define M68K_IVEC_LEVEL2_AUTOVECTOR	26
#define M68K_IVEC_LEVEL3_AUTOVECTOR	27
#define M68K_IVEC_LEVEL4_AUTOVECTOR	28
#define M68K_IVEC_LEVEL5_AUTOVECTOR	29
#define M68K_IVEC_LEVEL6_AUTOVECTOR	30
#define M68K_IVEC_LEVEL7_AUTOVECTOR	31

#define M68K_IVEC_TRAP0			32
#define M68K_IVEC_TRAP1			33
#define M68K_IVEC_TRAP2			34
#define M68K_IVEC_TRAP3			35
#define M68K_IVEC_TRAP4			36
#define M68K_IVEC_TRAP5			37
#define M68K_IVEC_TRAP6			38
#define M68K_IVEC_TRAP7			39
#define M68K_IVEC_TRAP8			40
#define M68K_IVEC_TRAP9			41
#define M68K_IVEC_TRAP10		42
#define M68K_IVEC_TRAP11		43
#define M68K_IVEC_TRAP12		44
#define M68K_IVEC_TRAP13		45
#define M68K_IVEC_TRAP14		46
#define M68K_IVEC_TRAP15		47
/*
 *	Unassigned, Reserved		48-59
 *
 * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR).
 */

/*
 * MC68302 Interrupt Vectors
 * Section 3.2
 */
enum m68302_ivec_e {
    M302_IVEC_ERR	=0,
    M302_IVEC_PB8	=1,	/* General-Purpose Interrupt 0 */
    M302_IVEC_SMC2	=2,
    M302_IVEC_SMC1	=3,
    M302_IVEC_TIMER3	=4,
    M302_IVEC_SCP	=5,
    M302_IVEC_TIMER2	=6,
    M302_IVEC_PB9	=7,	/* General-Purpose Interrupt 1 */
    M302_IVEC_SCC3	=8,
    M302_IVEC_TIMER1	=9,
    M302_IVEC_SCC2	=10,
    M302_IVEC_IDMA	=11,
    M302_IVEC_SDMA	=12,	/* SDMA Channels Bus Error */
    M302_IVEC_SCC1	=13,
    M302_IVEC_PB10	=14,	/* General-Purpose Interrupt 2 */
    M302_IVEC_PB11	=15,	/* General-Purpose Interrupt 3 */
    M302_IVEC_IRQ1	=17,	/* External Device */
    M302_IVEC_IRQ6	=22,	/* External Device */
    M302_IVEC_IRQ7	=23	/* External Device */
};


/*
 * GIMR - Global Interrupt Mode Register
 * Section 3.2.5.1
 */
#define RBIT_GIMR_MOD		(1<<15)
#define RBIT_GIMR_IV7		(1<<14)
#define RBIT_GIMR_IV6		(1<<13)
#define RBIT_GIMR_IV1		(1<<12)
#define RBIT_GIMR_ET7		(1<<10)
#define RBIT_GIMR_ET6		(1<<9)
#define RBIT_GIMR_ET1		(1<<8)
#define RBIT_GIMR_VECTOR	(7<<5)

/*
 * IPR - Interrupt Pending Register    (Section 3.2.5.2)
 * IMR - Interrupt Mask Register       (Section 3.2.5.3)
 * ISR - Interrupt In-Service Register (Section 3.2.5.4)
 */
#define RBIT_IPR_PB11		(1<<15)
#define RBIT_IPR_PB10		(1<<14)
#define RBIT_IPR_SCC1		(1<<13)
#define RBIT_IPR_SDMA		(1<<12)
#define RBIT_IPR_IDMA		(1<<11)
#define RBIT_IPR_SCC2		(1<<10)
#define RBIT_IPR_TIMER1		(1<<9)
#define RBIT_IPR_SCC3		(1<<8)
#define RBIT_IPR_PB9		(1<<7)
#define RBIT_IPR_TIMER2		(1<<6)
#define RBIT_IPR_SCP		(1<<5)
#define RBIT_IPR_TIMER3		(1<<4)
#define RBIT_IPR_SMC1		(1<<3)
#define RBIT_IPR_SMC2		(1<<2)
#define RBIT_IPR_PB8		(1<<1)
#define RBIT_IPR_ERR		(1<<0)

#define RBIT_ISR_PB11		(1<<15)
#define RBIT_ISR_PB10		(1<<14)
#define RBIT_ISR_SCC1		(1<<13)
#define RBIT_ISR_SDMA		(1<<12)
#define RBIT_ISR_IDMA		(1<<11)
#define RBIT_ISR_SCC2		(1<<10)
#define RBIT_ISR_TIMER1		(1<<9)
#define RBIT_ISR_SCC3		(1<<8)
#define RBIT_ISR_PB9		(1<<7)
#define RBIT_ISR_TIMER2		(1<<6)
#define RBIT_ISR_SCP		(1<<5)
#define RBIT_ISR_TIMER3		(1<<4)
#define RBIT_ISR_SMC1		(1<<3)
#define RBIT_ISR_SMC2		(1<<2)
#define RBIT_ISR_PB8		(1<<1)

#define RBIT_IMR_PB11		(1<<15)		/* PB11   Interrupt Mask */
#define RBIT_IMR_PB10		(1<<14)		/* PB10   Interrupt Mask */
#define RBIT_IMR_SCC1		(1<<13)		/* SCC1   Interrupt Mask */
#define RBIT_IMR_SDMA		(1<<12)		/* SDMA   Interrupt Mask */
#define RBIT_IMR_IDMA		(1<<11)		/* IDMA   Interrupt Mask */
#define RBIT_IMR_SCC2		(1<<10)		/* SCC2   Interrupt Mask */
#define RBIT_IMR_TIMER1		(1<<9)		/* TIMER1 Interrupt Mask */
#define RBIT_IMR_SCC3		(1<<8)		/* SCC3   Interrupt Mask */
#define RBIT_IMR_PB9		(1<<7)		/* PB9    Interrupt Mask */
#define RBIT_IMR_TIMER2		(1<<6)		/* TIMER2 Interrupt Mask */
#define RBIT_IMR_SCP		(1<<5)		/* SCP    Interrupt Mask */
#define RBIT_IMR_TIMER3		(1<<4)		/* TIMER3 Interrupt Mask */
#define RBIT_IMR_SMC1		(1<<3)		/* SMC1   Interrupt Mask */
#define RBIT_IMR_SMC2		(1<<2)		/* SMC2   Interrupt Mask */
#define RBIT_IMR_PB8		(1<<1)		/* PB8    Interrupt Mask */


/*
 * DRAM Refresh
 * Section 3.9
 *
 * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7
 * structures in the parameter RAM.
 *
 * Access to the DRAM registers can be accomplished by 
 * the following approach:
 *
 *	volatile m302_DRAM_refresh_t *dram;
 *	dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6];
 *
 * Then simply use pointer references (e.g. dram->count = 3).
 */
typedef struct {
    rtems_unsigned16	dram_high;	/* DRAM high address and FC */
    rtems_unsigned16	dram_low;	/* DRAM low address */
    rtems_unsigned16	increment;	/* increment step (bytes/row) */
    rtems_unsigned16	count;		/* RAM refresh cycle count (#rows) */
    rtems_unsigned16	t_ptr_h;	/* temporary refresh high addr & FC */
    rtems_unsigned16	t_ptr_l;	/* temporary refresh low address */
    rtems_unsigned16	t_count;	/* temporary refresh cycles count */
    rtems_unsigned16	res;		/* reserved */
} m302_DRAM_refresh_t;


/*
 * TMR - Timer Mode Register (for timers 1 and 2)
 * Section 3.5.2.1
 */
#define RBIT_TMR_ICLK_STOP	(0<<1)
#define RBIT_TMR_ICLK_MASTER	(1<<1)
#define RBIT_TMR_ICLK_MASTER16	(2<<1)
#define RBIT_TMR_ICLK_TIN	(3<<1)

#define RBIT_TMR_OM		(1<<5)
#define RBIT_TMR_ORI		(1<<4)
#define RBIT_TMR_FRR		(1<<3)
#define RBIT_TMR_RST		(1<<0)


/*
 * TER - Timer Event Register (for timers 1 and 2)
 * Section 3.5.2.5
 */
#define RBIT_TER_REF	(1<<1)		/* Output Reference Event */
#define RBIT_TER_CAP	(1<<0)		/* Capture Event */


/*
 * SCC Buffer Descriptors and Buffer Descriptors Table
 * Section 4.5.5
 */
typedef struct m302_SCC_bd {
    rtems_unsigned16 status;			/* status and control */
    rtems_unsigned16 length;			/* data length */
    volatile rtems_unsigned8  *buffer;		/* data buffer pointer */
} m302_SCC_bd_t;

typedef struct {
    m302_SCC_bd_t	rx[8];		/* receive buffer descriptors */
    m302_SCC_bd_t	tx[8];		/* transmit buffer descriptors */
} m302_SCC_bd_table_t;


/*
 * SCC Parameter RAM (offset 0x080 from an SCC Base)
 * Section 4.5.6
 *
 * Each SCC parameter RAM area begins at offset 0x80 from each SCC base
 * area (0x400, 0x500, or 0x600 from the dual-port RAM base).
 *
 * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific
 * portion of the SCC parameter RAM.
 */
typedef struct {
    rtems_unsigned8	rfcr;		/* Rx Function Code */
    rtems_unsigned8	tfcr;		/* Tx Function Code */
    rtems_unsigned16	mrblr;		/* Maximum Rx Buffer Length */
    rtems_unsigned16	_rstate;	/* Rx Internal State */
    rtems_unsigned8	res2;
    rtems_unsigned8	rbd;		/* Rx Internal Buffer Number */
    rtems_unsigned32	_rdptr;		/* Rx Internal Data Pointer */
    rtems_unsigned16	_rcount;	/* Rx Internal Byte Count */
    rtems_unsigned16	_rtmp;		/* Rx Temp */
    rtems_unsigned16	_tstate;	/* Tx Internal State */
    rtems_unsigned8	res7;
    rtems_unsigned8	tbd;		/* Tx Internal Buffer Number */
    rtems_unsigned32	_tdptr;		/* Tx Internal Data Pointer */
    rtems_unsigned16	_tcount;	/* Tx Internal Byte Count */
    rtems_unsigned16	_ttmp;		/* Tx Temp */
} m302_SCC_parameters_t;

/*
 * UART-Specific SCC Parameter RAM
 * Section 4.5.11.3
 */
typedef struct {
    rtems_unsigned16	max_idl;	/* Maximum IDLE Characters (rx) */
    rtems_unsigned16	idlc;		/* Temporary rx IDLE counter */
    rtems_unsigned16	brkcr;		/* Break Count Register (tx) */
    rtems_unsigned16	parec;		/* Receive Parity Error Counter */
    rtems_unsigned16	frmec;		/* Receive Framing Error Counter */
    rtems_unsigned16	nosec;		/* Receive Noise Counter */
    rtems_unsigned16	brkec;		/* Receive Break Condition Counter */
    rtems_unsigned16	uaddr1;		/* UART ADDRESS Character 1 */
    rtems_unsigned16	uaddr2;		/* UART ADDRESS Character 2 */
    rtems_unsigned16	rccr;		/* Receive Control Character Register */