m68360.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

/*
 **************************************************************************
 **************************************************************************
 **                                                                      **
 **  MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)  **
 **                                                                      **
 **                        HARDWARE DECLARATIONS                         **
 **                                                                      **
 **                                                                      **
 **  Submitted By:                                                       **
 **                                                                      **
 **      W. Eric Norum                                                   **
 **      Saskatchewan Accelerator Laboratory                             **
 **      University of Saskatchewan                                      **
 **      107 North Road                                                  **
 **      Saskatoon, Saskatchewan, CANADA                                 **
 **      S7N 5C6                                                         **
 **                                                                      **
 **      [e-mail]                                           **
 **                                                                      **
 **  $Id: m68360.h,v 1.6 2003/02/06 17:46:19 joel Exp $                                                                **
 **                                                                      **
 **************************************************************************
 **************************************************************************
 */

#ifndef __MC68360_h
#define __MC68360_h

/*
 *************************************************************************
 *                         REGISTER SUBBLOCKS                            *
 *************************************************************************
 */

/*
 * Memory controller registers
 */
typedef struct m360MEMCRegisters_ {
	unsigned long		br;
	unsigned long		or;
	unsigned long		_pad[2];
} m360MEMCRegisters_t;

/*
 * Serial Communications Controller registers
 */
typedef struct m360SCCRegisters_ {
	unsigned long		gsmr_l;
	unsigned long		gsmr_h;
	unsigned short		psmr;
	unsigned short		_pad0;
	unsigned short		todr;
	unsigned short		dsr;
	unsigned short		scce;
	unsigned short		_pad1;
	unsigned short		sccm;
	unsigned char		_pad2;
	unsigned char		sccs;
	unsigned long		_pad3[2];
} m360SCCRegisters_t;

/*
 * Serial Management Controller registers
 */
typedef struct m360SMCRegisters_ {
	unsigned short		_pad0;
	unsigned short		smcmr;
	unsigned short		_pad1;
	unsigned char		smce;
	unsigned char		_pad2;
	unsigned short		_pad3;
	unsigned char		smcm;
	unsigned char		_pad4;
	unsigned long		_pad5;
} m360SMCRegisters_t;


/*
 *************************************************************************
 *                         Miscellaneous Parameters                      *
 *************************************************************************
 */
typedef struct m360MiscParms_ {
	unsigned short		rev_num;
	unsigned short		_res1;
	unsigned long		_res2;
	unsigned long		_res3;
} m360MiscParms_t;

/*
 *************************************************************************
 *                              RISC Timers                              *
 *************************************************************************
 */
typedef struct m360TimerParms_ {
	unsigned short		tm_base;
	unsigned short		_tm_ptr;
	unsigned short		_r_tmr;
	unsigned short		_r_tmv;
	unsigned long		tm_cmd;
	unsigned long		tm_cnt;
} m360TimerParms_t;

/*
 * RISC Controller Configuration Register (RCCR)
 * All other bits in this register are either reserved or
 * used only with a Motorola-supplied RAM microcode packge.
 */
#define M360_RCCR_TIME		(1<<15)	/* Enable timer */
#define M360_RCCR_TIMEP(x)	((x)<<8)	/* Timer period */

/*
 * Command register
 * Set up this register before issuing a M360_CR_OP_SET_TIMER command.
 */
#define M360_TM_CMD_V		(1<<31)		/* Set to enable timer */
#define M360_TM_CMD_R		(1<<30)		/* Set for automatic restart */
#define M360_TM_CMD_TIMER(x)	((x)<<16)	/* Select timer */
#define M360_TM_CMD_PERIOD(x)	(x)		/* Timer period (16 bits) */

/*
 *************************************************************************
 *                               DMA Controllers                         *
 *************************************************************************
 */
typedef struct m360IDMAparms_ {
	unsigned short		ibase;
	unsigned short		ibptr;
	unsigned long		_istate;
	unsigned long		_itemp;
} m360IDMAparms_t;

/*
 *************************************************************************
 *                   Serial Communication Controllers                    *
 *************************************************************************
 */
typedef struct m360SCCparms_ {
	unsigned short		rbase;
	unsigned short		tbase;
	unsigned char		rfcr;
	unsigned char		tfcr;
	unsigned short		mrblr;
	unsigned long		_rstate;
	unsigned long		_pad0;
	unsigned short		_rbptr;
	unsigned short		_pad1;
	unsigned long		_pad2;
	unsigned long		_tstate;
	unsigned long		_pad3;
	unsigned short		_tbptr;
	unsigned short		_pad4;
	unsigned long		_pad5;
	unsigned long		_rcrc;
	unsigned long		_tcrc;
	union {
		struct {
			unsigned long		_res0;
			unsigned long		_res1;
			unsigned short		max_idl;
			unsigned short		_idlc;
			unsigned short		brkcr;
			unsigned short		parec;
			unsigned short		frmec;
			unsigned short		nosec;
			unsigned short		brkec;
			unsigned short		brklen;
			unsigned short		uaddr[2];
			unsigned short		_rtemp;
			unsigned short		toseq;
			unsigned short		character[8];
			unsigned short		rccm;
			unsigned short		rccr;
			unsigned short		rlbc;
		} uart;
		struct {
			unsigned long		crc_p;
			unsigned long		crc_c;
		} transparent;

	} un;
} m360SCCparms_t;

typedef struct m360SCCENparms_ {
	unsigned short		rbase;
	unsigned short		tbase;
	unsigned char		rfcr;
	unsigned char		tfcr;
	unsigned short		mrblr;
	unsigned long		_rstate;
	unsigned long		_pad0;
	unsigned short		_rbptr;
	unsigned short		_pad1;
	unsigned long		_pad2;
	unsigned long		_tstate;
	unsigned long		_pad3;
	unsigned short		_tbptr;
	unsigned short		_pad4;
	unsigned long		_pad5;
	unsigned long		_rcrc;
	unsigned long		_tcrc;
	union {
		struct {
			unsigned long		_res0;
			unsigned long		_res1;
			unsigned short		max_idl;
			unsigned short		_idlc;
			unsigned short		brkcr;
			unsigned short		parec;
			unsigned short		frmec;
			unsigned short		nosec;
			unsigned short		brkec;
			unsigned short		brklen;
			unsigned short		uaddr[2];
			unsigned short		_rtemp;
			unsigned short		toseq;
			unsigned short		character[8];
			unsigned short		rccm;
			unsigned short		rccr;
			unsigned short		rlbc;
		} uart;
		struct {
			unsigned long		c_pres;
			unsigned long		c_mask;
			unsigned long		crcec;
			unsigned long		alec;
			unsigned long		disfc;
			unsigned short		pads;
			unsigned short		ret_lim;
			unsigned short		_ret_cnt;
			unsigned short		mflr;
			unsigned short		minflr;
			unsigned short		maxd1;
			unsigned short		maxd2;
			unsigned short		_maxd;
			unsigned short		dma_cnt;
			unsigned short		_max_b;
			unsigned short		gaddr1;
			unsigned short		gaddr2;
			unsigned short		gaddr3;
			unsigned short		gaddr4;
			unsigned long		_tbuf0data0;
			unsigned long		_tbuf0data1;
			unsigned long		_tbuf0rba0;
			unsigned long		_tbuf0crc;
			unsigned short		_tbuf0bcnt;
			unsigned short		paddr_h;
			unsigned short		paddr_m;
			unsigned short		paddr_l;
			unsigned short		p_per;
			unsigned short		_rfbd_ptr;
			unsigned short		_tfbd_ptr;
			unsigned short		_tlbd_ptr;
			unsigned long		_tbuf1data0;
			unsigned long		_tbuf1data1;
			unsigned long		_tbuf1rba0;
			unsigned long		_tbuf1crc;
			unsigned short		_tbuf1bcnt;
			unsigned short		_tx_len;
			unsigned short		iaddr1;
			unsigned short		iaddr2;
			unsigned short		iaddr3;
			unsigned short		iaddr4;
			unsigned short		_boff_cnt;
			unsigned short		taddr_h;
			unsigned short		taddr_m;
			unsigned short		taddr_l;
		} ethernet;
		struct {
			unsigned long		crc_p;
			unsigned long		crc_c;
		} transparent;
	} un;
} m360SCCENparms_t;

/*
 * Receive and transmit function code register bits
 * These apply to the function code registers of all devices, not just SCC.
 */
#define M360_RFCR_MOT		(1<<4)
#define M360_RFCR_DMA_SPACE	0x8
#define M360_TFCR_MOT		(1<<4)
#define M360_TFCR_DMA_SPACE	0x8

/*
 *************************************************************************
 *                     Serial Management Controllers                     *
 *************************************************************************
 */
typedef struct m360SMCparms_ {
	unsigned short		rbase;
	unsigned short		tbase;
	unsigned char		rfcr;
	unsigned char		tfcr;
	unsigned short		mrblr;
	unsigned long		_rstate;
	unsigned long		_pad0;
	unsigned short		_rbptr;
	unsigned short		_pad1;
	unsigned long		_pad2;
	unsigned long		_tstate;
	unsigned long		_pad3;
	unsigned short		_tbptr;
	unsigned short		_pad4;
	unsigned long		_pad5;
	union {
		struct {
			unsigned short		max_idl;
			unsigned short		_pad0;
			unsigned short		brklen;
			unsigned short		brkec;
			unsigned short		brkcr;
			unsigned short		_r_mask;
		} uart;
		struct {
			unsigned short		_pad0[5];
		} transparent;
	} un;
} m360SMCparms_t;

/*
 * Mode register
 */
#define M360_SMCMR_CLEN(x)		((x)<<11)	/* Character length */
#define M360_SMCMR_2STOP		(1<<10)	/* 2 stop bits */
#define M360_SMCMR_PARITY		(1<<9)	/* Enable parity */
#define M360_SMCMR_EVEN			(1<<8)	/* Even parity */
#define M360_SMCMR_SM_GCI		(0<<4)	/* GCI Mode */
#define M360_SMCMR_SM_UART		(2<<4)	/* UART Mode */
#define M360_SMCMR_SM_TRANSPARENT	(3<<4)	/* Transparent Mode */
#define M360_SMCMR_DM_LOOPBACK		(1<<2)	/* Local loopback mode */
#define M360_SMCMR_DM_ECHO		(2<<2)	/* Echo mode */
#define M360_SMCMR_TEN			(1<<1)	/* Enable transmitter */
#define M360_SMCMR_REN			(1<<0)	/* Enable receiver */

/*
 * Event and mask registers (SMCE, SMCM)
 */
#define M360_SMCE_BRK	(1<<4)
#define M360_SMCE_BSY	(1<<2)
#define M360_SMCE_TX	(1<<1)
#define M360_SMCE_RX	(1<<0)

/*
 *************************************************************************
 *                      Serial Peripheral Interface                      *
 *************************************************************************
 */
typedef struct m360SPIparms_ {
	unsigned short		rbase;
	unsigned short		tbase;
	unsigned char		rfcr;
	unsigned char		tfcr;
	unsigned short		mrblr;
	unsigned long		_rstate;
	unsigned long		_pad0;
	unsigned short		_rbptr;
	unsigned short		_pad1;
	unsigned long		_pad2;
	unsigned long		_tstate;
	unsigned long		_pad3;
	unsigned short		_tbptr;
	unsigned short		_pad4;
	unsigned long		_pad5;
} m360SPIparms_t;

/*
 * Mode register (SPMODE)
 */
#define M360_SPMODE_LOOP		(1<<14)	/* Local loopback mode */
#define M360_SPMODE_CI			(1<<13)	/* Clock invert */
#define M360_SPMODE_CP			(1<<12)	/* Clock phase */
#define M360_SPMODE_DIV16		(1<<11)	/* Divide BRGCLK by 16 */
#define M360_SPMODE_REV			(1<<10)	/* Reverse data */
#define M360_SPMODE_MASTER		(1<<9)	/* SPI is master */
#define M360_SPMODE_EN			(1<<8)	/* Enable SPI */
#define M360_SPMODE_CLEN(x)		((x)<<4)	/* Character length */
#define M360_SPMODE_PM(x)		(x)	/* Prescaler modulus */

/*
 * Mode register (SPCOM)
 */
#define M360_SPCOM_STR			(1<<7)	/* Start transmit */

/*
 * Event and mask registers (SPIE, SPIM)
 */
#define M360_SPIE_MME	(1<<5)		/* Multi-master error */
#define M360_SPIE_TXE	(1<<4)		/* Tx error */
#define M360_SPIE_BSY	(1<<2)		/* Busy condition*/
#define M360_SPIE_TXB	(1<<1)		/* Tx buffer */
#define M360_SPIE_RXB	(1<<0)		/* Rx buffer */

/*
 *************************************************************************
 *                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
 *************************************************************************
 */
typedef struct m360BufferDescriptor_ {
	unsigned short		status;
	unsigned short		length;
	volatile void		*buffer;
} m360BufferDescriptor_t;

/*
 * Bits in receive buffer descriptor status word
 */
#define M360_BD_EMPTY		(1<<15)	/* Ethernet, SCC UART, SMC UART, SPI */
#define M360_BD_WRAP		(1<<13)	/* Ethernet, SCC UART, SMC UART, SPI */
#define M360_BD_INTERRUPT	(1<<12)	/* Ethernet, SCC UART, SMC UART, SPI */
#define M360_BD_LAST		(1<<11)	/* Ethernet, SPI */
#define M360_BD_CONTROL_CHAR	(1<<11)	/* SCC UART */
#define M360_BD_FIRST_IN_FRAME	(1<<10)	/* Ethernet */
#define M360_BD_ADDRESS		(1<<10)	/* SCC UART */
#define M360_BD_CONTINUOUS	(1<<9)	/* SCC UART, SMC UART, SPI */
#define M360_BD_MISS		(1<<8)	/* Ethernet */
#define M360_BD_IDLE		(1<<8)	/* SCC UART, SMC UART */
#define M360_BD_ADDRSS_MATCH	(1<<7)	/* SCC UART */
#define M360_BD_LONG		(1<<5)	/* Ethernet */
#define M360_BD_BREAK		(1<<5)	/* SCC UART, SMC UART */
#define M360_BD_NONALIGNED	(1<<4)	/* Ethernet */
#define M360_BD_FRAMING_ERROR	(1<<4)	/* SCC UART, SMC UART */
#define M360_BD_SHORT		(1<<3)	/* Ethernet */
#define M360_BD_PARITY_ERROR	(1<<3)	/* SCC UART, SMC UART */
#define M360_BD_CRC_ERROR	(1<<2)	/* Ethernet */
#define M360_BD_OVERRUN		(1<<1)	/* Ethernet, SCC UART, SMC UART, SPI */
#define M360_BD_COLLISION	(1<<0)	/* Ethernet */
#define M360_BD_CARRIER_LOST	(1<<0)	/* SCC UART */
#define M360_BD_MASTER_ERROR	(1<<0)	/* SPI */

/*
 * Bits in transmit buffer descriptor status word
 * Many bits have the same meaning as those in receiver buffer descriptors.
 */
#define M360_BD_READY		(1<<15)	/* Ethernet, SCC UART, SMC UART, SPI */
#define M360_BD_PAD		(1<<14)	/* Ethernet */
#define M360_BD_CTS_REPORT	(1<<11)	/* SCC UART */
#define M360_BD_TX_CRC		(1<<10)	/* Ethernet */
#define M360_BD_DEFER		(1<<9)	/* Ethernet */
#define M360_BD_HEARTBEAT	(1<<8)	/* Ethernet */
#define M360_BD_PREAMBLE	(1<<8)	/* SCC UART, SMC UART */
#define M360_BD_LATE_COLLISION	(1<<7)	/* Ethernet */
#define M360_BD_NO_STOP_BIT	(1<<7)	/* SCC UART */
#define M360_BD_RETRY_LIMIT	(1<<6)	/* Ethernet */